1 /*
2 * generic mmc spi driver
3 *
4 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
5 * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9 #include <errno.h>
10 #include <log.h>
11 #include <malloc.h>
12 #include <part.h>
13 #include <mmc.h>
14 #include <stdlib.h>
15 #include <linux/bitops.h>
16 #include <u-boot/crc.h>
17 #include <linux/crc7.h>
18 #include <asm/byteorder.h>
19 #include <dm.h>
20 #include <spi.h>
21
22 /* MMC/SD in SPI mode reports R1 status always */
23 #define R1_SPI_IDLE BIT(0)
24 #define R1_SPI_ERASE_RESET BIT(1)
25 #define R1_SPI_ILLEGAL_COMMAND BIT(2)
26 #define R1_SPI_COM_CRC BIT(3)
27 #define R1_SPI_ERASE_SEQ BIT(4)
28 #define R1_SPI_ADDRESS BIT(5)
29 #define R1_SPI_PARAMETER BIT(6)
30 /* R1 bit 7 is always zero, reuse this bit for error */
31 #define R1_SPI_ERROR BIT(7)
32
33 /* Response tokens used to ack each block written: */
34 #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
35 #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
36 #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
37 #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
38
39 /*
40 * Read and write blocks start with these tokens and end with crc;
41 * on error, read tokens act like a subset of R2_SPI_* values.
42 */
43 /* single block write multiblock read */
44 #define SPI_TOKEN_SINGLE 0xfe
45 /* multiblock write */
46 #define SPI_TOKEN_MULTI_WRITE 0xfc
47 /* terminate multiblock write */
48 #define SPI_TOKEN_STOP_TRAN 0xfd
49
50 /* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
51 #define MMC_SPI_CMD(x) (0x40 | (x))
52
53 /* bus capability */
54 #define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
55 #define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
56 #define MMC_SPI_MAX_CLOCK 25000000 /* SD/MMC legacy speed */
57
58 /* timeout value */
59 #define CMD_TIMEOUT 8
60 #define READ_TIMEOUT 3000000 /* 1 sec */
61 #define WRITE_TIMEOUT 3000000 /* 1 sec */
62 #define R1B_TIMEOUT 3000000 /* 1 sec */
63
64 struct mmc_spi_plat {
65 struct mmc_config cfg;
66 struct mmc mmc;
67 };
68
69 struct mmc_spi_priv {
70 struct spi_slave *spi;
71 };
72
73 /**
74 * mmc_spi_sendcmd() - send a command to the SD card
75 *
76 * @dev: mmc_spi device
77 * @cmdidx: command index
78 * @cmdarg: command argument
79 * @resp_type: card response type
80 * @resp: buffer to store the card response
81 * @resp_size: size of the card response
82 * @resp_match: if true, compare each of received bytes with @resp_match_value
83 * @resp_match_value: a value to be compared with each of received bytes
84 * @r1b: if true, receive additional bytes for busy signal token
85 * Return: 0 if OK, -ETIMEDOUT if no card response is received, -ve on error
86 */
mmc_spi_sendcmd(struct udevice * dev,ushort cmdidx,u32 cmdarg,u32 resp_type,u8 * resp,u32 resp_size,bool resp_match,u8 resp_match_value,bool r1b)87 static int mmc_spi_sendcmd(struct udevice *dev,
88 ushort cmdidx, u32 cmdarg, u32 resp_type,
89 u8 *resp, u32 resp_size,
90 bool resp_match, u8 resp_match_value, bool r1b)
91 {
92 int i, rpos = 0, ret = 0;
93 u8 cmdo[7], r;
94
95 if (!resp || !resp_size)
96 return 0;
97
98 debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
99 "resp_size=%d resp_match=%d resp_match_value=0x%x\n",
100 __func__, cmdidx, cmdarg, resp_type,
101 resp_size, resp_match, resp_match_value);
102
103 cmdo[0] = 0xff;
104 cmdo[1] = MMC_SPI_CMD(cmdidx);
105 cmdo[2] = cmdarg >> 24;
106 cmdo[3] = cmdarg >> 16;
107 cmdo[4] = cmdarg >> 8;
108 cmdo[5] = cmdarg;
109 cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
110 ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
111 if (ret)
112 return ret;
113
114 ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
115 if (ret)
116 return ret;
117
118 debug("%s: cmd%d", __func__, cmdidx);
119
120 if (resp_match)
121 r = ~resp_match_value;
122 i = CMD_TIMEOUT;
123 while (i) {
124 ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
125 if (ret)
126 return ret;
127 debug(" resp%d=0x%x", rpos, r);
128 rpos++;
129 i--;
130
131 if (resp_match) {
132 if (r == resp_match_value)
133 break;
134 } else {
135 if (!(r & 0x80))
136 break;
137 }
138
139 if (!i)
140 return -ETIMEDOUT;
141 }
142
143 resp[0] = r;
144 for (i = 1; i < resp_size; i++) {
145 ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
146 if (ret)
147 return ret;
148 debug(" resp%d=0x%x", rpos, r);
149 rpos++;
150 resp[i] = r;
151 }
152
153 if (r1b == true) {
154 i = R1B_TIMEOUT;
155 while (i) {
156 ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
157 if (ret)
158 return ret;
159
160 debug(" resp%d=0x%x", rpos, r);
161 rpos++;
162 i--;
163
164 if (r)
165 break;
166 }
167 if (!i)
168 return -ETIMEDOUT;
169 }
170
171 debug("\n");
172
173 return 0;
174 }
175
176 /**
177 * mmc_spi_readdata() - read data block(s) from the SD card
178 *
179 * @dev: mmc_spi device
180 * @xbuf: buffer of the actual data (excluding token and crc) to read
181 * @bcnt: number of data blocks to transfer
182 * @bsize: size of the actual data (excluding token and crc) in bytes
183 * Return: 0 if OK, -ECOMM if crc error, -ETIMEDOUT on other errors
184 */
mmc_spi_readdata(struct udevice * dev,void * xbuf,u32 bcnt,u32 bsize)185 static int mmc_spi_readdata(struct udevice *dev,
186 void *xbuf, u32 bcnt, u32 bsize)
187 {
188 u16 crc;
189 u8 *buf = xbuf, r1;
190 int i, ret = 0;
191
192 while (bcnt--) {
193 for (i = 0; i < READ_TIMEOUT; i++) {
194 ret = dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
195 if (ret)
196 return ret;
197 if (r1 == SPI_TOKEN_SINGLE)
198 break;
199 }
200 debug("%s: data tok%d 0x%x\n", __func__, i, r1);
201 if (r1 == SPI_TOKEN_SINGLE) {
202 ret = dm_spi_xfer(dev, bsize * 8, NULL, buf, 0);
203 if (ret)
204 return ret;
205 ret = dm_spi_xfer(dev, 2 * 8, NULL, &crc, 0);
206 if (ret)
207 return ret;
208 #ifdef CONFIG_MMC_SPI_CRC_ON
209 u16 crc_ok = be16_to_cpu(crc16_ccitt(0, buf, bsize));
210 if (crc_ok != crc) {
211 debug("%s: data crc error, expected %04x got %04x\n",
212 __func__, crc_ok, crc);
213 r1 = R1_SPI_COM_CRC;
214 break;
215 }
216 #endif
217 r1 = 0;
218 } else {
219 r1 = R1_SPI_ERROR;
220 break;
221 }
222 buf += bsize;
223 }
224
225 if (r1 & R1_SPI_COM_CRC)
226 ret = -ECOMM;
227 else if (r1) /* other errors */
228 ret = -ETIMEDOUT;
229
230 return ret;
231 }
232
233 /**
234 * mmc_spi_writedata() - write data block(s) to the SD card
235 *
236 * @dev: mmc_spi device
237 * @xbuf: buffer of the actual data (excluding token and crc) to write
238 * @bcnt: number of data blocks to transfer
239 * @bsize: size of actual data (excluding token and crc) in bytes
240 * @multi: indicate a transfer by multiple block write command (CMD25)
241 * Return: 0 if OK, -ECOMM if crc error, -ETIMEDOUT on other errors
242 */
mmc_spi_writedata(struct udevice * dev,const void * xbuf,u32 bcnt,u32 bsize,int multi)243 static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
244 u32 bcnt, u32 bsize, int multi)
245 {
246 const u8 *buf = xbuf;
247 u8 r1, tok[2];
248 u16 crc;
249 int i, ret = 0;
250
251 tok[0] = 0xff;
252 tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
253
254 while (bcnt--) {
255 #ifdef CONFIG_MMC_SPI_CRC_ON
256 crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
257 #endif
258 dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
259 dm_spi_xfer(dev, bsize * 8, buf, NULL, 0);
260 dm_spi_xfer(dev, 2 * 8, &crc, NULL, 0);
261 for (i = 0; i < CMD_TIMEOUT; i++) {
262 dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
263 if ((r1 & 0x10) == 0) /* response token */
264 break;
265 }
266 debug("%s: data tok%d 0x%x\n", __func__, i, r1);
267 if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
268 debug("%s: data accepted\n", __func__);
269 for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
270 dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
271 if (i && r1 == 0xff) {
272 r1 = 0;
273 break;
274 }
275 }
276 if (i == WRITE_TIMEOUT) {
277 debug("%s: data write timeout 0x%x\n",
278 __func__, r1);
279 r1 = R1_SPI_ERROR;
280 break;
281 }
282 } else {
283 debug("%s: data error 0x%x\n", __func__, r1);
284 r1 = R1_SPI_COM_CRC;
285 break;
286 }
287 buf += bsize;
288 }
289 if (multi && bcnt == -1) { /* stop multi write */
290 tok[1] = SPI_TOKEN_STOP_TRAN;
291 dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
292 for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
293 dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
294 if (i && r1 == 0xff) {
295 r1 = 0;
296 break;
297 }
298 }
299 if (i == WRITE_TIMEOUT) {
300 debug("%s: data write timeout 0x%x\n", __func__, r1);
301 r1 = R1_SPI_ERROR;
302 }
303 }
304
305 if (r1 & R1_SPI_COM_CRC)
306 ret = -ECOMM;
307 else if (r1) /* other errors */
308 ret = -ETIMEDOUT;
309
310 return ret;
311 }
312
dm_mmc_spi_set_ios(struct udevice * dev)313 static int dm_mmc_spi_set_ios(struct udevice *dev)
314 {
315 return 0;
316 }
317
dm_mmc_spi_request(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)318 static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
319 struct mmc_data *data)
320 {
321 int i, multi, ret = 0;
322 u8 *resp = NULL;
323 u32 resp_size = 0;
324 bool resp_match = false, r1b = false;
325 u8 resp8 = 0, resp16[2] = { 0 }, resp40[5] = { 0 }, resp_match_value = 0;
326
327 dm_spi_claim_bus(dev);
328
329 for (i = 0; i < 4; i++)
330 cmd->response[i] = 0;
331
332 switch (cmd->cmdidx) {
333 case SD_CMD_APP_SEND_OP_COND:
334 case MMC_CMD_SEND_OP_COND:
335 resp = &resp8;
336 resp_size = sizeof(resp8);
337 cmd->cmdarg = 0x40000000;
338 break;
339 case SD_CMD_SEND_IF_COND:
340 resp = (u8 *)&resp40[0];
341 resp_size = sizeof(resp40);
342 resp_match = true;
343 resp_match_value = R1_SPI_IDLE;
344 break;
345 case MMC_CMD_SPI_READ_OCR:
346 resp = (u8 *)&resp40[0];
347 resp_size = sizeof(resp40);
348 break;
349 case MMC_CMD_SEND_STATUS:
350 resp = (u8 *)&resp16[0];
351 resp_size = sizeof(resp16);
352 break;
353 case MMC_CMD_SET_BLOCKLEN:
354 case MMC_CMD_SPI_CRC_ON_OFF:
355 resp = &resp8;
356 resp_size = sizeof(resp8);
357 resp_match = true;
358 resp_match_value = 0x0;
359 break;
360 case MMC_CMD_STOP_TRANSMISSION:
361 case MMC_CMD_ERASE:
362 resp = &resp8;
363 resp_size = sizeof(resp8);
364 r1b = true;
365 break;
366 case MMC_CMD_SEND_CSD:
367 case MMC_CMD_SEND_CID:
368 case MMC_CMD_READ_SINGLE_BLOCK:
369 case MMC_CMD_READ_MULTIPLE_BLOCK:
370 case MMC_CMD_WRITE_SINGLE_BLOCK:
371 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
372 case MMC_CMD_APP_CMD:
373 case SD_CMD_ERASE_WR_BLK_START:
374 case SD_CMD_ERASE_WR_BLK_END:
375 resp = &resp8;
376 resp_size = sizeof(resp8);
377 break;
378 default:
379 resp = &resp8;
380 resp_size = sizeof(resp8);
381 resp_match = true;
382 resp_match_value = R1_SPI_IDLE;
383 break;
384 };
385
386 ret = mmc_spi_sendcmd(dev, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
387 resp, resp_size, resp_match, resp_match_value, r1b);
388 if (ret)
389 goto done;
390
391 switch (cmd->cmdidx) {
392 case SD_CMD_APP_SEND_OP_COND:
393 case MMC_CMD_SEND_OP_COND:
394 cmd->response[0] = (resp8 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
395 break;
396 case SD_CMD_SEND_IF_COND:
397 case MMC_CMD_SPI_READ_OCR:
398 cmd->response[0] = resp40[4];
399 cmd->response[0] |= (uint)resp40[3] << 8;
400 cmd->response[0] |= (uint)resp40[2] << 16;
401 cmd->response[0] |= (uint)resp40[1] << 24;
402 break;
403 case MMC_CMD_SEND_STATUS:
404 if (resp16[0] || resp16[1])
405 cmd->response[0] = MMC_STATUS_ERROR;
406 else
407 cmd->response[0] = MMC_STATUS_RDY_FOR_DATA;
408 break;
409 case MMC_CMD_SEND_CID:
410 case MMC_CMD_SEND_CSD:
411 ret = mmc_spi_readdata(dev, cmd->response, 1, 16);
412 if (ret)
413 return ret;
414 for (i = 0; i < 4; i++)
415 cmd->response[i] =
416 cpu_to_be32(cmd->response[i]);
417 break;
418 default:
419 cmd->response[0] = resp8;
420 break;
421 }
422
423 debug("%s: cmd%d resp0=0x%x resp1=0x%x resp2=0x%x resp3=0x%x\n",
424 __func__, cmd->cmdidx, cmd->response[0], cmd->response[1],
425 cmd->response[2], cmd->response[3]);
426
427 if (data) {
428 debug("%s: data flags=0x%x blocks=%d block_size=%d\n",
429 __func__, data->flags, data->blocks, data->blocksize);
430 multi = (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK);
431 if (data->flags == MMC_DATA_READ)
432 ret = mmc_spi_readdata(dev, data->dest,
433 data->blocks, data->blocksize);
434 else if (data->flags == MMC_DATA_WRITE)
435 ret = mmc_spi_writedata(dev, data->src,
436 data->blocks, data->blocksize,
437 multi);
438 }
439
440 done:
441 dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
442
443 dm_spi_release_bus(dev);
444
445 return ret;
446 }
447
mmc_spi_probe(struct udevice * dev)448 static int mmc_spi_probe(struct udevice *dev)
449 {
450 struct mmc_spi_priv *priv = dev_get_priv(dev);
451 struct mmc_spi_plat *plat = dev_get_plat(dev);
452 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
453 char *name;
454
455 priv->spi = dev_get_parent_priv(dev);
456 if (!priv->spi->max_hz)
457 priv->spi->max_hz = MMC_SPI_MAX_CLOCK;
458 priv->spi->mode = SPI_MODE_0;
459 priv->spi->wordlen = 8;
460
461 name = malloc(strlen(dev->parent->name) + strlen(dev->name) + 4);
462 if (!name)
463 return -ENOMEM;
464 sprintf(name, "%s:%s", dev->parent->name, dev->name);
465
466 plat->cfg.name = name;
467 plat->cfg.host_caps = MMC_MODE_SPI;
468 plat->cfg.voltages = MMC_SPI_VOLTAGE;
469 plat->cfg.f_min = MMC_SPI_MIN_CLOCK;
470 plat->cfg.f_max = priv->spi->max_hz;
471 plat->cfg.part_type = PART_TYPE_DOS;
472 plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
473
474 plat->mmc.cfg = &plat->cfg;
475 plat->mmc.priv = priv;
476 plat->mmc.dev = dev;
477
478 upriv->mmc = &plat->mmc;
479
480 return 0;
481 }
482
mmc_spi_bind(struct udevice * dev)483 static int mmc_spi_bind(struct udevice *dev)
484 {
485 struct mmc_spi_plat *plat = dev_get_plat(dev);
486
487 return mmc_bind(dev, &plat->mmc, &plat->cfg);
488 }
489
490 static const struct dm_mmc_ops mmc_spi_ops = {
491 .send_cmd = dm_mmc_spi_request,
492 .set_ios = dm_mmc_spi_set_ios,
493 };
494
495 static const struct udevice_id dm_mmc_spi_match[] = {
496 { .compatible = "mmc-spi-slot" },
497 { /* sentinel */ }
498 };
499
500 U_BOOT_DRIVER(mmc_spi) = {
501 .name = "mmc_spi",
502 .id = UCLASS_MMC,
503 .of_match = dm_mmc_spi_match,
504 .ops = &mmc_spi_ops,
505 .probe = mmc_spi_probe,
506 .bind = mmc_spi_bind,
507 .plat_auto = sizeof(struct mmc_spi_plat),
508 .priv_auto = sizeof(struct mmc_spi_priv),
509 };
510