1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 SAMSUNG Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Jaehoon Chung <jh80.chung@samsung.com>
6 * Portions Copyright 2011-2019 NVIDIA Corporation
7 */
8
9 #include <bouncebuf.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <log.h>
13 #include <mmc.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <asm/arch-tegra/tegra_mmc.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
21 #include <asm/arch/clock.h>
22 #endif
23
24 struct tegra_mmc_plat {
25 struct mmc_config cfg;
26 struct mmc mmc;
27 };
28
29 struct tegra_mmc_priv {
30 struct tegra_mmc *reg;
31 struct reset_ctl reset_ctl;
32 struct clk clk;
33 struct gpio_desc cd_gpio; /* Change Detect GPIO */
34 struct gpio_desc pwr_gpio; /* Power GPIO */
35 struct gpio_desc wp_gpio; /* Write Protect GPIO */
36 unsigned int version; /* SDHCI spec. version */
37 unsigned int clock; /* Current clock (MHz) */
38 int mmc_id; /* peripheral id */
39
40 int tap_value;
41 int trim_value;
42 };
43
tegra_mmc_set_power(struct tegra_mmc_priv * priv,unsigned short power)44 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
45 unsigned short power)
46 {
47 u8 pwr = 0;
48 debug("%s: power = %x\n", __func__, power);
49
50 if (power != (unsigned short)-1) {
51 switch (1 << power) {
52 case MMC_VDD_165_195:
53 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
54 break;
55 case MMC_VDD_29_30:
56 case MMC_VDD_30_31:
57 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
58 break;
59 case MMC_VDD_32_33:
60 case MMC_VDD_33_34:
61 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
62 break;
63 }
64 }
65 debug("%s: pwr = %X\n", __func__, pwr);
66
67 /* Set the bus voltage first (if any) */
68 writeb(pwr, &priv->reg->pwrcon);
69 if (pwr == 0)
70 return;
71
72 /* Now enable bus power */
73 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
74 writeb(pwr, &priv->reg->pwrcon);
75 }
76
tegra_mmc_prepare_data(struct tegra_mmc_priv * priv,struct mmc_data * data,struct bounce_buffer * bbstate)77 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
78 struct mmc_data *data,
79 struct bounce_buffer *bbstate)
80 {
81 unsigned char ctrl;
82
83 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
84 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
85 data->blocksize);
86
87 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
88 /*
89 * DMASEL[4:3]
90 * 00 = Selects SDMA
91 * 01 = Reserved
92 * 10 = Selects 32-bit Address ADMA2
93 * 11 = Selects 64-bit Address ADMA2
94 */
95 ctrl = readb(&priv->reg->hostctl);
96 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
97 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
98 writeb(ctrl, &priv->reg->hostctl);
99
100 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
101 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
102 writew(data->blocks, &priv->reg->blkcnt);
103 }
104
tegra_mmc_set_transfer_mode(struct tegra_mmc_priv * priv,struct mmc_data * data)105 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
106 struct mmc_data *data)
107 {
108 unsigned short mode;
109 debug(" mmc_set_transfer_mode called\n");
110 /*
111 * TRNMOD
112 * MUL1SIN0[5] : Multi/Single Block Select
113 * RD1WT0[4] : Data Transfer Direction Select
114 * 1 = read
115 * 0 = write
116 * ENACMD12[2] : Auto CMD12 Enable
117 * ENBLKCNT[1] : Block Count Enable
118 * ENDMA[0] : DMA Enable
119 */
120 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
121 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
122
123 if (data->blocks > 1)
124 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
125
126 if (data->flags & MMC_DATA_READ)
127 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
128
129 writew(mode, &priv->reg->trnmod);
130 }
131
tegra_mmc_wait_inhibit(struct tegra_mmc_priv * priv,struct mmc_cmd * cmd,struct mmc_data * data,unsigned int timeout)132 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
133 struct mmc_cmd *cmd,
134 struct mmc_data *data,
135 unsigned int timeout)
136 {
137 /*
138 * PRNSTS
139 * CMDINHDAT[1] : Command Inhibit (DAT)
140 * CMDINHCMD[0] : Command Inhibit (CMD)
141 */
142 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
143
144 /*
145 * We shouldn't wait for data inhibit for stop commands, even
146 * though they might use busy signaling
147 */
148 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
149 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
150
151 while (readl(&priv->reg->prnsts) & mask) {
152 if (timeout == 0) {
153 printf("%s: timeout error\n", __func__);
154 return -1;
155 }
156 timeout--;
157 udelay(1000);
158 }
159
160 return 0;
161 }
162
tegra_mmc_send_cmd_bounced(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data,struct bounce_buffer * bbstate)163 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
164 struct mmc_data *data,
165 struct bounce_buffer *bbstate)
166 {
167 struct tegra_mmc_priv *priv = dev_get_priv(dev);
168 int flags, i;
169 int result;
170 unsigned int mask = 0;
171 unsigned int retry = 0x100000;
172 debug(" mmc_send_cmd called\n");
173
174 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
175
176 if (result < 0)
177 return result;
178
179 if (data)
180 tegra_mmc_prepare_data(priv, data, bbstate);
181
182 debug("cmd->arg: %08x\n", cmd->cmdarg);
183 writel(cmd->cmdarg, &priv->reg->argument);
184
185 if (data)
186 tegra_mmc_set_transfer_mode(priv, data);
187
188 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
189 return -1;
190
191 /*
192 * CMDREG
193 * CMDIDX[13:8] : Command index
194 * DATAPRNT[5] : Data Present Select
195 * ENCMDIDX[4] : Command Index Check Enable
196 * ENCMDCRC[3] : Command CRC Check Enable
197 * RSPTYP[1:0]
198 * 00 = No Response
199 * 01 = Length 136
200 * 10 = Length 48
201 * 11 = Length 48 Check busy after response
202 */
203 if (!(cmd->resp_type & MMC_RSP_PRESENT))
204 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
205 else if (cmd->resp_type & MMC_RSP_136)
206 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
207 else if (cmd->resp_type & MMC_RSP_BUSY)
208 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
209 else
210 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
211
212 if (cmd->resp_type & MMC_RSP_CRC)
213 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
214 if (cmd->resp_type & MMC_RSP_OPCODE)
215 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
216 if (data)
217 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
218
219 debug("cmd: %d\n", cmd->cmdidx);
220
221 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
222
223 for (i = 0; i < retry; i++) {
224 mask = readl(&priv->reg->norintsts);
225 /* Command Complete */
226 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
227 if (!data)
228 writel(mask, &priv->reg->norintsts);
229 break;
230 }
231 }
232
233 if (i == retry) {
234 printf("%s: waiting for status update\n", __func__);
235 writel(mask, &priv->reg->norintsts);
236 return -ETIMEDOUT;
237 }
238
239 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
240 /* Timeout Error */
241 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
242 writel(mask, &priv->reg->norintsts);
243 return -ETIMEDOUT;
244 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
245 /* Error Interrupt */
246 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
247 writel(mask, &priv->reg->norintsts);
248 return -1;
249 }
250
251 if (cmd->resp_type & MMC_RSP_PRESENT) {
252 if (cmd->resp_type & MMC_RSP_136) {
253 /* CRC is stripped so we need to do some shifting. */
254 for (i = 0; i < 4; i++) {
255 unsigned long offset = (unsigned long)
256 (&priv->reg->rspreg3 - i);
257 cmd->response[i] = readl(offset) << 8;
258
259 if (i != 3) {
260 cmd->response[i] |=
261 readb(offset - 1);
262 }
263 debug("cmd->resp[%d]: %08x\n",
264 i, cmd->response[i]);
265 }
266 } else if (cmd->resp_type & MMC_RSP_BUSY) {
267 for (i = 0; i < retry; i++) {
268 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
269 if (readl(&priv->reg->prnsts)
270 & (1 << 20)) /* DAT[0] */
271 break;
272 }
273
274 if (i == retry) {
275 printf("%s: card is still busy\n", __func__);
276 writel(mask, &priv->reg->norintsts);
277 return -ETIMEDOUT;
278 }
279
280 cmd->response[0] = readl(&priv->reg->rspreg0);
281 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
282 } else {
283 cmd->response[0] = readl(&priv->reg->rspreg0);
284 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
285 }
286 }
287
288 if (data) {
289 unsigned long start = get_timer(0);
290
291 while (1) {
292 mask = readl(&priv->reg->norintsts);
293
294 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
295 /* Error Interrupt */
296 writel(mask, &priv->reg->norintsts);
297 printf("%s: error during transfer: 0x%08x\n",
298 __func__, mask);
299 return -1;
300 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
301 /*
302 * DMA Interrupt, restart the transfer where
303 * it was interrupted.
304 */
305 unsigned int address = readl(&priv->reg->sysad);
306
307 debug("DMA end\n");
308 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
309 &priv->reg->norintsts);
310 writel(address, &priv->reg->sysad);
311 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
312 /* Transfer Complete */
313 debug("r/w is done\n");
314 break;
315 } else if (get_timer(start) > 8000UL) {
316 writel(mask, &priv->reg->norintsts);
317 printf("%s: MMC Timeout\n"
318 " Interrupt status 0x%08x\n"
319 " Interrupt status enable 0x%08x\n"
320 " Interrupt signal enable 0x%08x\n"
321 " Present status 0x%08x\n",
322 __func__, mask,
323 readl(&priv->reg->norintstsen),
324 readl(&priv->reg->norintsigen),
325 readl(&priv->reg->prnsts));
326 return -1;
327 }
328 }
329 writel(mask, &priv->reg->norintsts);
330 }
331
332 udelay(1000);
333 return 0;
334 }
335
tegra_mmc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)336 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
337 struct mmc_data *data)
338 {
339 void *buf;
340 unsigned int bbflags;
341 size_t len;
342 struct bounce_buffer bbstate;
343 int ret;
344
345 if (data) {
346 if (data->flags & MMC_DATA_READ) {
347 buf = data->dest;
348 bbflags = GEN_BB_WRITE;
349 } else {
350 buf = (void *)data->src;
351 bbflags = GEN_BB_READ;
352 }
353 len = data->blocks * data->blocksize;
354
355 bounce_buffer_start(&bbstate, buf, len, bbflags);
356 }
357
358 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
359
360 if (data)
361 bounce_buffer_stop(&bbstate);
362
363 return ret;
364 }
365
tegra_mmc_change_clock(struct tegra_mmc_priv * priv,uint clock)366 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
367 {
368 ulong rate;
369 int div;
370 unsigned short clk;
371 unsigned long timeout;
372
373 debug(" mmc_change_clock called\n");
374
375 /*
376 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
377 */
378 if (clock == 0)
379 goto out;
380
381 rate = clk_set_rate(&priv->clk, clock);
382 div = (rate + clock - 1) / clock;
383
384 #if defined(CONFIG_TEGRA210)
385 if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
386 /* clock_adjust_periph_pll_div() chooses a 'bad' clock
387 * on SDMMC1 T210, so skip it here and force a clock
388 * that's been spec'd in the table in the TRM for
389 * card-detect (400KHz).
390 */
391 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
392 CLOCK_ID_PERIPH, 24727273, NULL);
393 div = 62;
394
395 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
396 __func__, effective_rate, div, clock);
397 } else {
398 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
399 clock, &div);
400 }
401 #endif
402 debug("div = %d\n", div);
403
404 writew(0, &priv->reg->clkcon);
405
406 /*
407 * CLKCON
408 * SELFREQ[15:8] : base clock divided by value
409 * ENSDCLK[2] : SD Clock Enable
410 * STBLINTCLK[1] : Internal Clock Stable
411 * ENINTCLK[0] : Internal Clock Enable
412 */
413 div >>= 1;
414 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
415 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
416 writew(clk, &priv->reg->clkcon);
417
418 /* Wait max 10 ms */
419 timeout = 10;
420 while (!(readw(&priv->reg->clkcon) &
421 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
422 if (timeout == 0) {
423 printf("%s: timeout error\n", __func__);
424 return;
425 }
426 timeout--;
427 udelay(1000);
428 }
429
430 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
431 writew(clk, &priv->reg->clkcon);
432
433 debug("mmc_change_clock: clkcon = %08X\n", clk);
434
435 out:
436 priv->clock = clock;
437 }
438
tegra_mmc_set_ios(struct udevice * dev)439 static int tegra_mmc_set_ios(struct udevice *dev)
440 {
441 struct tegra_mmc_priv *priv = dev_get_priv(dev);
442 struct mmc *mmc = mmc_get_mmc_dev(dev);
443 unsigned char ctrl;
444 debug(" mmc_set_ios called\n");
445
446 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
447
448 /* Change clock first */
449 tegra_mmc_change_clock(priv, mmc->clock);
450
451 ctrl = readb(&priv->reg->hostctl);
452
453 /*
454 * WIDE8[5]
455 * 0 = Depend on WIDE4
456 * 1 = 8-bit mode
457 * WIDE4[1]
458 * 1 = 4-bit mode
459 * 0 = 1-bit mode
460 */
461 if (mmc->bus_width == 8)
462 ctrl |= (1 << 5);
463 else if (mmc->bus_width == 4)
464 ctrl |= (1 << 1);
465 else
466 ctrl &= ~(1 << 1 | 1 << 5);
467
468 writeb(ctrl, &priv->reg->hostctl);
469 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
470
471 return 0;
472 }
473
tegra_mmc_pad_init(struct tegra_mmc_priv * priv)474 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
475 {
476 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
477 u32 val;
478 u16 clk_con;
479 int timeout;
480 int id = priv->mmc_id;
481
482 debug("%s: sdmmc address = %p, id = %d\n", __func__,
483 priv->reg, id);
484
485 /* Set the pad drive strength for SDMMC1 or 3 only */
486 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
487 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
488 __func__);
489 return;
490 }
491
492 val = readl(&priv->reg->sdmemcmppadctl);
493 val &= 0xFFFFFFF0;
494 val |= MEMCOMP_PADCTRL_VREF;
495 writel(val, &priv->reg->sdmemcmppadctl);
496
497 /* Disable SD Clock Enable before running auto-cal as per TRM */
498 clk_con = readw(&priv->reg->clkcon);
499 debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
500 clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
501 writew(clk_con, &priv->reg->clkcon);
502
503 val = readl(&priv->reg->autocalcfg);
504 val &= 0xFFFF0000;
505 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
506 writel(val, &priv->reg->autocalcfg);
507 val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
508 writel(val, &priv->reg->autocalcfg);
509 debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
510 udelay(1);
511 timeout = 100; /* 10 mSec max (100*100uS) */
512 do {
513 val = readl(&priv->reg->autocalsts);
514 udelay(100);
515 } while ((val & AUTO_CAL_ACTIVE) && --timeout);
516 val = readl(&priv->reg->autocalsts);
517 debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
518 __func__, val, timeout);
519
520 /* Re-enable SD Clock Enable when auto-cal is done */
521 clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
522 writew(clk_con, &priv->reg->clkcon);
523 clk_con = readw(&priv->reg->clkcon);
524 debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
525
526 if (timeout == 0) {
527 printf("%s: Warning: Autocal timed out!\n", __func__);
528 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
529 }
530 #endif /* T30/T210 */
531 }
532
tegra_mmc_reset(struct tegra_mmc_priv * priv,struct mmc * mmc)533 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
534 {
535 unsigned int timeout;
536 debug(" mmc_reset called\n");
537
538 /*
539 * RSTALL[0] : Software reset for all
540 * 1 = reset
541 * 0 = work
542 */
543 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
544
545 priv->clock = 0;
546
547 /* Wait max 100 ms */
548 timeout = 100;
549
550 /* hw clears the bit when it's done */
551 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
552 if (timeout == 0) {
553 printf("%s: timeout error\n", __func__);
554 return;
555 }
556 timeout--;
557 udelay(1000);
558 }
559
560 /* Set SD bus voltage & enable bus power */
561 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
562 debug("%s: power control = %02X, host control = %02X\n", __func__,
563 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
564
565 /* Make sure SDIO pads are set up */
566 tegra_mmc_pad_init(priv);
567
568 if (!IS_ERR_VALUE(priv->tap_value) ||
569 !IS_ERR_VALUE(priv->trim_value)) {
570 u32 val;
571
572 val = readl(&priv->reg->venclkctl);
573
574 val &= ~TRIM_VAL_MASK;
575 val |= (priv->trim_value << TRIM_VAL_SHIFT);
576
577 val &= ~TAP_VAL_MASK;
578 val |= (priv->tap_value << TAP_VAL_SHIFT);
579
580 writel(val, &priv->reg->venclkctl);
581 debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
582 }
583 }
584
tegra_mmc_init(struct udevice * dev)585 static int tegra_mmc_init(struct udevice *dev)
586 {
587 struct tegra_mmc_priv *priv = dev_get_priv(dev);
588 struct mmc *mmc = mmc_get_mmc_dev(dev);
589 unsigned int mask;
590 debug(" tegra_mmc_init called\n");
591
592 #if defined(CONFIG_TEGRA210)
593 priv->mmc_id = clock_decode_periph_id(dev);
594 if (priv->mmc_id == PERIPH_ID_NONE) {
595 printf("%s: Missing/invalid peripheral ID\n", __func__);
596 return -EINVAL;
597 }
598 #endif
599 tegra_mmc_reset(priv, mmc);
600
601 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
602 /*
603 * Disable the external clock loopback and use the internal one on
604 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
605 * bits being set to 0xfffd according to the TRM.
606 *
607 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
608 * approach once proper kernel integration made it mainline.
609 */
610 if (priv->reg == (void *)0x700b0400) {
611 mask = readl(&priv->reg->venmiscctl);
612 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
613 writel(mask, &priv->reg->venmiscctl);
614 }
615 #endif
616
617 priv->version = readw(&priv->reg->hcver);
618 debug("host version = %x\n", priv->version);
619
620 /* mask all */
621 writel(0xffffffff, &priv->reg->norintstsen);
622 writel(0xffffffff, &priv->reg->norintsigen);
623
624 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
625 /*
626 * NORMAL Interrupt Status Enable Register init
627 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
628 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
629 * [3] ENSTADMAINT : DMA boundary interrupt
630 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
631 * [0] ENSTACMDCMPLT : Command Complete Status Enable
632 */
633 mask = readl(&priv->reg->norintstsen);
634 mask &= ~(0xffff);
635 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
636 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
637 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
638 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
639 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
640 writel(mask, &priv->reg->norintstsen);
641
642 /*
643 * NORMAL Interrupt Signal Enable Register init
644 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
645 */
646 mask = readl(&priv->reg->norintsigen);
647 mask &= ~(0xffff);
648 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
649 writel(mask, &priv->reg->norintsigen);
650
651 return 0;
652 }
653
tegra_mmc_getcd(struct udevice * dev)654 static int tegra_mmc_getcd(struct udevice *dev)
655 {
656 struct tegra_mmc_priv *priv = dev_get_priv(dev);
657
658 debug("tegra_mmc_getcd called\n");
659
660 if (dm_gpio_is_valid(&priv->cd_gpio))
661 return dm_gpio_get_value(&priv->cd_gpio);
662
663 return 1;
664 }
665
666 static const struct dm_mmc_ops tegra_mmc_ops = {
667 .send_cmd = tegra_mmc_send_cmd,
668 .set_ios = tegra_mmc_set_ios,
669 .get_cd = tegra_mmc_getcd,
670 };
671
tegra_mmc_probe(struct udevice * dev)672 static int tegra_mmc_probe(struct udevice *dev)
673 {
674 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
675 struct tegra_mmc_plat *plat = dev_get_plat(dev);
676 struct tegra_mmc_priv *priv = dev_get_priv(dev);
677 struct mmc_config *cfg = &plat->cfg;
678 int bus_width, ret;
679
680 cfg->name = dev->name;
681
682 bus_width = dev_read_u32_default(dev, "bus-width", 1);
683
684 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
685 cfg->host_caps = 0;
686 if (bus_width == 8)
687 cfg->host_caps |= MMC_MODE_8BIT;
688 if (bus_width >= 4)
689 cfg->host_caps |= MMC_MODE_4BIT;
690 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
691
692 /*
693 * min freq is for card identification, and is the highest
694 * low-speed SDIO card frequency (actually 400KHz)
695 * max freq is highest HS eMMC clock as per the SD/MMC spec
696 * (actually 52MHz)
697 */
698 cfg->f_min = 375000;
699 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 48000000);
700
701 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
702
703 priv->reg = dev_read_addr_ptr(dev);
704
705 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
706 if (ret) {
707 debug("reset_get_by_name() failed: %d\n", ret);
708 return ret;
709 }
710 ret = clk_get_by_index(dev, 0, &priv->clk);
711 if (ret) {
712 debug("clk_get_by_index() failed: %d\n", ret);
713 return ret;
714 }
715
716 ret = reset_assert(&priv->reset_ctl);
717 if (ret)
718 return ret;
719 ret = clk_enable(&priv->clk);
720 if (ret)
721 return ret;
722 ret = clk_set_rate(&priv->clk, 20000000);
723 if (IS_ERR_VALUE(ret))
724 return ret;
725 ret = reset_deassert(&priv->reset_ctl);
726 if (ret)
727 return ret;
728
729 /* These GPIOs are optional */
730 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
731 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
732 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
733 GPIOD_IS_OUT);
734 if (dm_gpio_is_valid(&priv->pwr_gpio))
735 dm_gpio_set_value(&priv->pwr_gpio, 1);
736
737 ret = dev_read_u32(dev, "nvidia,default-tap", &priv->tap_value);
738 if (ret)
739 priv->tap_value = ret;
740
741 ret = dev_read_u32(dev, "nvidia,default-trim", &priv->trim_value);
742 if (ret)
743 priv->trim_value = ret;
744
745 upriv->mmc = &plat->mmc;
746
747 return tegra_mmc_init(dev);
748 }
749
tegra_mmc_bind(struct udevice * dev)750 static int tegra_mmc_bind(struct udevice *dev)
751 {
752 struct tegra_mmc_plat *plat = dev_get_plat(dev);
753
754 return mmc_bind(dev, &plat->mmc, &plat->cfg);
755 }
756
757 static const struct udevice_id tegra_mmc_ids[] = {
758 { .compatible = "nvidia,tegra20-sdhci" },
759 { .compatible = "nvidia,tegra30-sdhci" },
760 { .compatible = "nvidia,tegra114-sdhci" },
761 { .compatible = "nvidia,tegra124-sdhci" },
762 { .compatible = "nvidia,tegra210-sdhci" },
763 { .compatible = "nvidia,tegra186-sdhci" },
764 { }
765 };
766
767 U_BOOT_DRIVER(tegra_mmc_drv) = {
768 .name = "tegra_mmc",
769 .id = UCLASS_MMC,
770 .of_match = tegra_mmc_ids,
771 .bind = tegra_mmc_bind,
772 .probe = tegra_mmc_probe,
773 .ops = &tegra_mmc_ops,
774 .plat_auto = sizeof(struct tegra_mmc_plat),
775 .priv_auto = sizeof(struct tegra_mmc_priv),
776 };
777