1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
5 */
6
7 /*
8 * Designware ethernet IP driver for U-Boot
9 */
10
11 #include <clk.h>
12 #include <cpu_func.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <eth_phy.h>
16 #include <log.h>
17 #include <miiphy.h>
18 #include <malloc.h>
19 #include <net.h>
20 #include <pci.h>
21 #include <reset.h>
22 #include <phys2bus.h>
23 #include <asm/cache.h>
24 #include <dm/device_compat.h>
25 #include <dm/device-internal.h>
26 #include <dm/devres.h>
27 #include <dm/lists.h>
28 #include <linux/compiler.h>
29 #include <linux/delay.h>
30 #include <linux/err.h>
31 #include <linux/kernel.h>
32 #include <asm/io.h>
33 #include <linux/printk.h>
34 #include <power/regulator.h>
35 #include "designware.h"
36 #if IS_ENABLED(CONFIG_ARCH_NPCM8XX)
37 #include <asm/arch/gmac.h>
38 #endif
39
dw_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)40 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
41 {
42 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
43 struct eth_mac_regs *mac_p = priv->mac_regs_p;
44 ulong start;
45 u16 miiaddr;
46 int timeout = CFG_MDIO_TIMEOUT;
47
48 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
49 ((reg << MIIREGSHIFT) & MII_REGMSK);
50
51 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
52
53 start = get_timer(0);
54 while (get_timer(start) < timeout) {
55 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
56 return readl(&mac_p->miidata);
57 udelay(10);
58 };
59
60 return -ETIMEDOUT;
61 }
62
dw_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)63 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
64 u16 val)
65 {
66 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
67 struct eth_mac_regs *mac_p = priv->mac_regs_p;
68 ulong start;
69 u16 miiaddr;
70 int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
71
72 writel(val, &mac_p->miidata);
73 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
74 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
75
76 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
77
78 start = get_timer(0);
79 while (get_timer(start) < timeout) {
80 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
81 ret = 0;
82 break;
83 }
84 udelay(10);
85 };
86
87 return ret;
88 }
89
90 #if CONFIG_IS_ENABLED(DM_GPIO)
__dw_mdio_reset(struct udevice * dev)91 static int __dw_mdio_reset(struct udevice *dev)
92 {
93 struct dw_eth_dev *priv = dev_get_priv(dev);
94 struct dw_eth_pdata *pdata = dev_get_plat(dev);
95 int ret;
96
97 if (!dm_gpio_is_valid(&priv->reset_gpio))
98 return 0;
99
100 /* reset the phy */
101 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
102 if (ret)
103 return ret;
104
105 udelay(pdata->reset_delays[0]);
106
107 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
108 if (ret)
109 return ret;
110
111 udelay(pdata->reset_delays[1]);
112
113 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
114 if (ret)
115 return ret;
116
117 udelay(pdata->reset_delays[2]);
118
119 return 0;
120 }
121
dw_mdio_reset(struct mii_dev * bus)122 static int dw_mdio_reset(struct mii_dev *bus)
123 {
124 struct udevice *dev = bus->priv;
125
126 return __dw_mdio_reset(dev);
127 }
128 #endif
129
130 #if IS_ENABLED(CONFIG_DM_MDIO)
designware_eth_mdio_read(struct udevice * mdio_dev,int addr,int devad,int reg)131 int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
132 {
133 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
134
135 return dw_mdio_read(pdata->mii_bus, addr, devad, reg);
136 }
137
designware_eth_mdio_write(struct udevice * mdio_dev,int addr,int devad,int reg,u16 val)138 int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
139 {
140 struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
141
142 return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
143 }
144
145 #if CONFIG_IS_ENABLED(DM_GPIO)
designware_eth_mdio_reset(struct udevice * mdio_dev)146 int designware_eth_mdio_reset(struct udevice *mdio_dev)
147 {
148 struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
149 struct udevice *dev = mdio_pdata->mii_bus->priv;
150
151 return __dw_mdio_reset(dev->parent);
152 }
153 #endif
154
155 static const struct mdio_ops designware_eth_mdio_ops = {
156 .read = designware_eth_mdio_read,
157 .write = designware_eth_mdio_write,
158 #if CONFIG_IS_ENABLED(DM_GPIO)
159 .reset = designware_eth_mdio_reset,
160 #endif
161 };
162
designware_eth_mdio_probe(struct udevice * dev)163 static int designware_eth_mdio_probe(struct udevice *dev)
164 {
165 /* Use the priv data of parent */
166 dev_set_priv(dev, dev_get_priv(dev->parent));
167
168 return 0;
169 }
170
171 U_BOOT_DRIVER(designware_eth_mdio) = {
172 .name = "eth_designware_mdio",
173 .id = UCLASS_MDIO,
174 .probe = designware_eth_mdio_probe,
175 .ops = &designware_eth_mdio_ops,
176 .plat_auto = sizeof(struct mdio_perdev_priv),
177 };
178 #endif
179
dw_mdio_init(const char * name,void * priv)180 static int dw_mdio_init(const char *name, void *priv)
181 {
182 struct mii_dev *bus = mdio_alloc();
183
184 if (!bus) {
185 printf("Failed to allocate MDIO bus\n");
186 return -ENOMEM;
187 }
188
189 bus->read = dw_mdio_read;
190 bus->write = dw_mdio_write;
191 snprintf(bus->name, sizeof(bus->name), "%s", name);
192 #if CONFIG_IS_ENABLED(DM_GPIO)
193 bus->reset = dw_mdio_reset;
194 #endif
195
196 bus->priv = priv;
197
198 return mdio_register(bus);
199 }
200
201 #if IS_ENABLED(CONFIG_DM_MDIO)
dw_dm_mdio_init(const char * name,void * priv)202 static int dw_dm_mdio_init(const char *name, void *priv)
203 {
204 struct udevice *dev = priv;
205 ofnode node;
206 int ret;
207
208 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
209 const char *subnode_name = ofnode_get_name(node);
210 struct udevice *mdiodev;
211
212 if (strcmp(subnode_name, "mdio"))
213 continue;
214
215 ret = device_bind_driver_to_node(dev, "eth_designware_mdio",
216 subnode_name, node, &mdiodev);
217 if (ret)
218 debug("%s: not able to bind mdio device node\n", __func__);
219
220 return 0;
221 }
222
223 printf("%s: mdio node is missing, registering legacy mdio bus", __func__);
224
225 return dw_mdio_init(name, priv);
226 }
227 #endif
228
229 #if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
dw_eth_bb_mdio_active(struct mii_dev * miidev)230 static int dw_eth_bb_mdio_active(struct mii_dev *miidev)
231 {
232 struct dw_eth_dev *priv = miidev->priv;
233 struct gpio_desc *desc = &priv->mdio_gpio;
234
235 desc->flags = 0;
236 dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
237
238 return 0;
239 }
240
dw_eth_bb_mdio_tristate(struct mii_dev * miidev)241 static int dw_eth_bb_mdio_tristate(struct mii_dev *miidev)
242 {
243 struct dw_eth_dev *priv = miidev->priv;
244 struct gpio_desc *desc = &priv->mdio_gpio;
245
246 desc->flags = 0;
247 dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);
248
249 return 0;
250 }
251
dw_eth_bb_set_mdio(struct mii_dev * miidev,int v)252 static int dw_eth_bb_set_mdio(struct mii_dev *miidev, int v)
253 {
254 struct dw_eth_dev *priv = miidev->priv;
255
256 if (v)
257 dm_gpio_set_value(&priv->mdio_gpio, 1);
258 else
259 dm_gpio_set_value(&priv->mdio_gpio, 0);
260
261 return 0;
262 }
263
dw_eth_bb_get_mdio(struct mii_dev * miidev,int * v)264 static int dw_eth_bb_get_mdio(struct mii_dev *miidev, int *v)
265 {
266 struct dw_eth_dev *priv = miidev->priv;
267
268 *v = dm_gpio_get_value(&priv->mdio_gpio);
269
270 return 0;
271 }
272
dw_eth_bb_set_mdc(struct mii_dev * miidev,int v)273 static int dw_eth_bb_set_mdc(struct mii_dev *miidev, int v)
274 {
275 struct dw_eth_dev *priv = miidev->priv;
276
277 if (v)
278 dm_gpio_set_value(&priv->mdc_gpio, 1);
279 else
280 dm_gpio_set_value(&priv->mdc_gpio, 0);
281
282 return 0;
283 }
284
dw_eth_bb_delay(struct mii_dev * miidev)285 static int dw_eth_bb_delay(struct mii_dev *miidev)
286 {
287 struct dw_eth_dev *priv = miidev->priv;
288
289 udelay(priv->bb_delay);
290 return 0;
291 }
292
293 static const struct bb_miiphy_bus_ops dw_eth_bb_miiphy_bus_ops = {
294 .mdio_active = dw_eth_bb_mdio_active,
295 .mdio_tristate = dw_eth_bb_mdio_tristate,
296 .set_mdio = dw_eth_bb_set_mdio,
297 .get_mdio = dw_eth_bb_get_mdio,
298 .set_mdc = dw_eth_bb_set_mdc,
299 .delay = dw_eth_bb_delay,
300 };
301
dw_bb_miiphy_read(struct mii_dev * miidev,int addr,int devad,int reg)302 static int dw_bb_miiphy_read(struct mii_dev *miidev, int addr,
303 int devad, int reg)
304 {
305 return bb_miiphy_read(miidev, &dw_eth_bb_miiphy_bus_ops,
306 addr, devad, reg);
307 }
308
dw_bb_miiphy_write(struct mii_dev * miidev,int addr,int devad,int reg,u16 value)309 static int dw_bb_miiphy_write(struct mii_dev *miidev, int addr,
310 int devad, int reg, u16 value)
311 {
312 return bb_miiphy_write(miidev, &dw_eth_bb_miiphy_bus_ops,
313 addr, devad, reg, value);
314 }
315
dw_bb_mdio_init(const char * name,struct udevice * dev)316 static int dw_bb_mdio_init(const char *name, struct udevice *dev)
317 {
318 struct dw_eth_dev *dwpriv = dev_get_priv(dev);
319 struct mii_dev *bus = mdio_alloc();
320 int ret;
321
322 if (!bus) {
323 printf("Failed to allocate MDIO bus\n");
324 return -ENOMEM;
325 }
326
327 debug("\n%s: use bitbang mii..\n", dev->name);
328 ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
329 &dwpriv->mdc_gpio,
330 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
331 if (ret) {
332 debug("no mdc-gpio\n");
333 return ret;
334 }
335 ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
336 &dwpriv->mdio_gpio,
337 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
338 if (ret) {
339 debug("no mdio-gpio\n");
340 return ret;
341 }
342 dwpriv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1);
343
344 dwpriv->bus = bus;
345 dwpriv->dev = dev;
346
347 snprintf(bus->name, sizeof(bus->name), "%s", name);
348 bus->read = dw_bb_miiphy_read;
349 bus->write = dw_bb_miiphy_write;
350 #if CONFIG_IS_ENABLED(DM_GPIO)
351 bus->reset = dw_mdio_reset;
352 #endif
353 bus->priv = dwpriv;
354
355 return mdio_register(bus);
356 }
357 #endif
358
tx_descs_init(struct dw_eth_dev * priv)359 static void tx_descs_init(struct dw_eth_dev *priv)
360 {
361 struct eth_dma_regs *dma_p = priv->dma_regs_p;
362 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
363 char *txbuffs = &priv->txbuffs[0];
364 struct dmamacdescr *desc_p;
365 u32 idx;
366
367 for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
368 desc_p = &desc_table_p[idx];
369 desc_p->dmamac_addr = dev_phys_to_bus(priv->dev,
370 (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]);
371 desc_p->dmamac_next = dev_phys_to_bus(priv->dev,
372 (ulong)&desc_table_p[idx + 1]);
373
374 #if defined(CONFIG_DW_ALTDESCRIPTOR)
375 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
376 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
377 DESC_TXSTS_TXCHECKINSCTRL |
378 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
379
380 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
381 desc_p->dmamac_cntl = 0;
382 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
383 #else
384 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
385 desc_p->txrx_status = 0;
386 #endif
387 }
388
389 /* Correcting the last pointer of the chain */
390 desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]);
391
392 /* Flush all Tx buffer descriptors at once */
393 flush_dcache_range((ulong)priv->tx_mac_descrtable,
394 (ulong)priv->tx_mac_descrtable +
395 sizeof(priv->tx_mac_descrtable));
396
397 writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]),
398 &dma_p->txdesclistaddr);
399 priv->tx_currdescnum = 0;
400 }
401
rx_descs_init(struct dw_eth_dev * priv)402 static void rx_descs_init(struct dw_eth_dev *priv)
403 {
404 struct eth_dma_regs *dma_p = priv->dma_regs_p;
405 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
406 char *rxbuffs = &priv->rxbuffs[0];
407 struct dmamacdescr *desc_p;
408 u32 idx;
409
410 /* Before passing buffers to GMAC we need to make sure zeros
411 * written there right after "priv" structure allocation were
412 * flushed into RAM.
413 * Otherwise there's a chance to get some of them flushed in RAM when
414 * GMAC is already pushing data to RAM via DMA. This way incoming from
415 * GMAC data will be corrupted. */
416 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
417
418 for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
419 desc_p = &desc_table_p[idx];
420 desc_p->dmamac_addr = dev_phys_to_bus(priv->dev,
421 (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]);
422 desc_p->dmamac_next = dev_phys_to_bus(priv->dev,
423 (ulong)&desc_table_p[idx + 1]);
424
425 desc_p->dmamac_cntl =
426 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
427 DESC_RXCTRL_RXCHAIN;
428
429 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
430 }
431
432 /* Correcting the last pointer of the chain */
433 desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]);
434
435 /* Flush all Rx buffer descriptors at once */
436 flush_dcache_range((ulong)priv->rx_mac_descrtable,
437 (ulong)priv->rx_mac_descrtable +
438 sizeof(priv->rx_mac_descrtable));
439
440 writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]),
441 &dma_p->rxdesclistaddr);
442 priv->rx_currdescnum = 0;
443 }
444
_dw_write_hwaddr(struct dw_eth_dev * priv,u8 * mac_id)445 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
446 {
447 struct eth_mac_regs *mac_p = priv->mac_regs_p;
448 u32 macid_lo, macid_hi;
449
450 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
451 (mac_id[3] << 24);
452 macid_hi = mac_id[4] + (mac_id[5] << 8);
453
454 writel(macid_hi, &mac_p->macaddr0hi);
455 writel(macid_lo, &mac_p->macaddr0lo);
456
457 return 0;
458 }
459
dw_adjust_link(struct dw_eth_dev * priv,struct eth_mac_regs * mac_p,struct phy_device * phydev)460 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
461 struct phy_device *phydev)
462 {
463 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
464
465 if (!phydev->link) {
466 printf("%s: No link.\n", phydev->dev->name);
467 return 0;
468 }
469
470 if (phydev->speed != 1000)
471 conf |= MII_PORTSELECT;
472 else
473 conf &= ~MII_PORTSELECT;
474
475 if (phydev->speed == 100)
476 conf |= FES_100;
477
478 if (phydev->duplex)
479 conf |= FULLDPLXMODE;
480
481 writel(conf, &mac_p->conf);
482
483 printf("Speed: %d, %s duplex%s\n", phydev->speed,
484 (phydev->duplex) ? "full" : "half",
485 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
486
487 #ifdef CONFIG_ARCH_NPCM8XX
488 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
489 ulong start;
490
491 /* Indirect access to VR_MII_MMD registers */
492 writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
493 /* Set PCS_Mode to SGMII */
494 clrsetbits_le16(PCS_BA + VR_MII_MMD_AN_CTRL, BIT(1), BIT(2));
495 /* Set Auto Speed Mode Change */
496 setbits_le16(PCS_BA + VR_MII_MMD_CTRL1, BIT(9));
497 /* Indirect access to SR_MII_MMD registers */
498 writew((SR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
499 /* Restart Auto-Negotiation */
500 setbits_le16(PCS_BA + SR_MII_MMD_CTRL, BIT(9) | BIT(12));
501
502 printf("SGMII PHY Wait for link up \n");
503 /* SGMII PHY Wait for link up */
504 start = get_timer(0);
505 while (!(readw(PCS_BA + SR_MII_MMD_STS) & BIT(2))) {
506 if (get_timer(start) >= LINK_UP_TIMEOUT) {
507 printf("PHY link up timeout\n");
508 return -ETIMEDOUT;
509 }
510 mdelay(1);
511 };
512 }
513 /* Pass all Multicast Frames */
514 setbits_le32(&mac_p->framefilt, BIT(4));
515 #endif
516
517 return 0;
518 }
519
_dw_eth_halt(struct dw_eth_dev * priv)520 static void _dw_eth_halt(struct dw_eth_dev *priv)
521 {
522 struct eth_mac_regs *mac_p = priv->mac_regs_p;
523 struct eth_dma_regs *dma_p = priv->dma_regs_p;
524
525 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
526 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
527
528 phy_shutdown(priv->phydev);
529 }
530
designware_eth_init(struct dw_eth_dev * priv,u8 * enetaddr)531 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
532 {
533 struct eth_mac_regs *mac_p = priv->mac_regs_p;
534 struct eth_dma_regs *dma_p = priv->dma_regs_p;
535 ulong start;
536 int ret;
537
538 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
539
540 /*
541 * When a MII PHY is used, we must set the PS bit for the DMA
542 * reset to succeed.
543 */
544 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
545 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
546 else
547 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
548
549 start = get_timer(0);
550 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
551 if (get_timer(start) >= CFG_MACRESET_TIMEOUT) {
552 printf("DMA reset timeout\n");
553 return -ETIMEDOUT;
554 }
555
556 mdelay(100);
557 };
558
559 /*
560 * Soft reset above clears HW address registers.
561 * So we have to set it here once again.
562 */
563 _dw_write_hwaddr(priv, enetaddr);
564
565 rx_descs_init(priv);
566 tx_descs_init(priv);
567
568 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
569
570 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
571 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
572 &dma_p->opmode);
573 #else
574 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
575 &dma_p->opmode);
576 #endif
577
578 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
579
580 #ifdef CONFIG_DW_AXI_BURST_LEN
581 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
582 #endif
583
584 /* Start up the PHY */
585 ret = phy_startup(priv->phydev);
586 if (ret) {
587 printf("Could not initialize PHY %s\n",
588 priv->phydev->dev->name);
589 return ret;
590 }
591
592 ret = dw_adjust_link(priv, mac_p, priv->phydev);
593 if (ret)
594 return ret;
595
596 return 0;
597 }
598
designware_eth_enable(struct dw_eth_dev * priv)599 int designware_eth_enable(struct dw_eth_dev *priv)
600 {
601 struct eth_mac_regs *mac_p = priv->mac_regs_p;
602
603 if (!priv->phydev->link)
604 return -EIO;
605
606 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
607
608 return 0;
609 }
610
611 #define ETH_ZLEN 60
612
_dw_eth_send(struct dw_eth_dev * priv,void * packet,int length)613 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
614 {
615 struct eth_dma_regs *dma_p = priv->dma_regs_p;
616 u32 desc_num = priv->tx_currdescnum;
617 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
618 ulong desc_start = (ulong)desc_p;
619 ulong desc_end = desc_start +
620 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
621 ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
622 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
623 /*
624 * Strictly we only need to invalidate the "txrx_status" field
625 * for the following check, but on some platforms we cannot
626 * invalidate only 4 bytes, so we flush the entire descriptor,
627 * which is 16 bytes in total. This is safe because the
628 * individual descriptors in the array are each aligned to
629 * ARCH_DMA_MINALIGN and padded appropriately.
630 */
631 invalidate_dcache_range(desc_start, desc_end);
632
633 /* Check if the descriptor is owned by CPU */
634 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
635 printf("CPU not owner of tx frame\n");
636 return -EPERM;
637 }
638
639 memcpy((void *)data_start, packet, length);
640 if (length < ETH_ZLEN) {
641 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
642 length = ETH_ZLEN;
643 }
644
645 /* Flush data to be sent */
646 flush_dcache_range(data_start, data_end);
647
648 #if defined(CONFIG_DW_ALTDESCRIPTOR)
649 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
650 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
651 ((length << DESC_TXCTRL_SIZE1SHFT) &
652 DESC_TXCTRL_SIZE1MASK);
653
654 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
655 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
656 #else
657 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
658 ((length << DESC_TXCTRL_SIZE1SHFT) &
659 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
660 DESC_TXCTRL_TXFIRST;
661
662 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
663 #endif
664
665 /* Flush modified buffer descriptor */
666 flush_dcache_range(desc_start, desc_end);
667
668 /* Test the wrap-around condition. */
669 if (++desc_num >= CFG_TX_DESCR_NUM)
670 desc_num = 0;
671
672 priv->tx_currdescnum = desc_num;
673
674 /* Start the transmission */
675 writel(POLL_DATA, &dma_p->txpolldemand);
676
677 return 0;
678 }
679
_dw_eth_recv(struct dw_eth_dev * priv,uchar ** packetp)680 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
681 {
682 u32 status, desc_num = priv->rx_currdescnum;
683 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
684 int length = -EAGAIN;
685 ulong desc_start = (ulong)desc_p;
686 ulong desc_end = desc_start +
687 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
688 ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
689 ulong data_end;
690
691 /* Invalidate entire buffer descriptor */
692 invalidate_dcache_range(desc_start, desc_end);
693
694 status = desc_p->txrx_status;
695
696 /* Check if the owner is the CPU */
697 if (!(status & DESC_RXSTS_OWNBYDMA)) {
698
699 length = (status & DESC_RXSTS_FRMLENMSK) >>
700 DESC_RXSTS_FRMLENSHFT;
701
702 /* Invalidate received data */
703 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
704 invalidate_dcache_range(data_start, data_end);
705 *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev,
706 desc_p->dmamac_addr);
707 }
708
709 return length;
710 }
711
_dw_free_pkt(struct dw_eth_dev * priv)712 static int _dw_free_pkt(struct dw_eth_dev *priv)
713 {
714 u32 desc_num = priv->rx_currdescnum;
715 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
716 ulong desc_start = (ulong)desc_p;
717 ulong desc_end = desc_start +
718 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
719 ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
720 ulong data_end = data_start + roundup(CFG_ETH_BUFSIZE, ARCH_DMA_MINALIGN);
721
722 /* Invalidate the descriptor buffer data */
723 invalidate_dcache_range(data_start, data_end);
724
725 /*
726 * Make the current descriptor valid again and go to
727 * the next one
728 */
729 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
730
731 /* Flush only status field - others weren't changed */
732 flush_dcache_range(desc_start, desc_end);
733
734 /* Test the wrap-around condition. */
735 if (++desc_num >= CFG_RX_DESCR_NUM)
736 desc_num = 0;
737 priv->rx_currdescnum = desc_num;
738
739 return 0;
740 }
741
dw_phy_init(struct dw_eth_dev * priv,void * dev)742 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
743 {
744 struct phy_device *phydev;
745 int ret;
746
747 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
748 eth_phy_set_mdio_bus(dev, NULL);
749
750 #if IS_ENABLED(CONFIG_DM_MDIO)
751 phydev = dm_eth_phy_connect(dev);
752 if (!phydev)
753 return -ENODEV;
754 #else
755 int phy_addr = -1;
756
757 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
758 phy_addr = eth_phy_get_addr(dev);
759
760 #ifdef CONFIG_PHY_ADDR
761 phy_addr = CONFIG_PHY_ADDR;
762 #endif
763
764 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
765 if (!phydev)
766 return -ENODEV;
767 #endif
768
769 phydev->supported &= PHY_GBIT_FEATURES;
770 if (priv->max_speed) {
771 ret = phy_set_supported(phydev, priv->max_speed);
772 if (ret)
773 return ret;
774 }
775 phydev->advertising = phydev->supported;
776
777 priv->phydev = phydev;
778 phy_config(phydev);
779
780 return 0;
781 }
782
designware_eth_start(struct udevice * dev)783 static int designware_eth_start(struct udevice *dev)
784 {
785 struct eth_pdata *pdata = dev_get_plat(dev);
786 struct dw_eth_dev *priv = dev_get_priv(dev);
787 int ret;
788
789 ret = designware_eth_init(priv, pdata->enetaddr);
790 if (ret)
791 return ret;
792 ret = designware_eth_enable(priv);
793 if (ret)
794 return ret;
795
796 return 0;
797 }
798
designware_eth_send(struct udevice * dev,void * packet,int length)799 int designware_eth_send(struct udevice *dev, void *packet, int length)
800 {
801 struct dw_eth_dev *priv = dev_get_priv(dev);
802
803 return _dw_eth_send(priv, packet, length);
804 }
805
designware_eth_recv(struct udevice * dev,int flags,uchar ** packetp)806 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
807 {
808 struct dw_eth_dev *priv = dev_get_priv(dev);
809
810 return _dw_eth_recv(priv, packetp);
811 }
812
designware_eth_free_pkt(struct udevice * dev,uchar * packet,int length)813 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
814 {
815 struct dw_eth_dev *priv = dev_get_priv(dev);
816
817 return _dw_free_pkt(priv);
818 }
819
designware_eth_stop(struct udevice * dev)820 void designware_eth_stop(struct udevice *dev)
821 {
822 struct dw_eth_dev *priv = dev_get_priv(dev);
823
824 return _dw_eth_halt(priv);
825 }
826
designware_eth_write_hwaddr(struct udevice * dev)827 int designware_eth_write_hwaddr(struct udevice *dev)
828 {
829 struct eth_pdata *pdata = dev_get_plat(dev);
830 struct dw_eth_dev *priv = dev_get_priv(dev);
831
832 return _dw_write_hwaddr(priv, pdata->enetaddr);
833 }
834
designware_eth_bind(struct udevice * dev)835 static int designware_eth_bind(struct udevice *dev)
836 {
837 if (IS_ENABLED(CONFIG_PCI)) {
838 static int num_cards;
839 char name[20];
840
841 /* Create a unique device name for PCI type devices */
842 if (device_is_on_pci_bus(dev)) {
843 sprintf(name, "eth_designware#%u", num_cards++);
844 device_set_name(dev, name);
845 }
846 }
847
848 return 0;
849 }
850
designware_eth_probe(struct udevice * dev)851 int designware_eth_probe(struct udevice *dev)
852 {
853 struct eth_pdata *pdata = dev_get_plat(dev);
854 struct dw_eth_dev *priv = dev_get_priv(dev);
855 phys_addr_t iobase = pdata->iobase;
856 void *ioaddr;
857 int ret, err;
858 struct reset_ctl_bulk reset_bulk;
859 #ifdef CONFIG_CLK
860 int i, clock_nb;
861
862 priv->clock_count = 0;
863 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
864 0);
865 if (clock_nb > 0) {
866 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
867 GFP_KERNEL);
868 if (!priv->clocks)
869 return -ENOMEM;
870
871 for (i = 0; i < clock_nb; i++) {
872 err = clk_get_by_index(dev, i, &priv->clocks[i]);
873 if (err < 0)
874 break;
875
876 err = clk_enable(&priv->clocks[i]);
877 if (err && err != -ENOSYS && err != -ENOTSUPP) {
878 pr_err("failed to enable clock %d\n", i);
879 goto clk_err;
880 }
881 priv->clock_count++;
882 }
883 } else if (clock_nb != -ENOENT) {
884 pr_err("failed to get clock phandle(%d)\n", clock_nb);
885 return clock_nb;
886 }
887 #endif
888
889 #if defined(CONFIG_DM_REGULATOR)
890 struct udevice *phy_supply;
891
892 ret = device_get_supply_regulator(dev, "phy-supply",
893 &phy_supply);
894 if (ret) {
895 debug("%s: No phy supply\n", dev->name);
896 } else {
897 ret = regulator_set_enable(phy_supply, true);
898 if (ret) {
899 puts("Error enabling phy supply\n");
900 return ret;
901 }
902 #if IS_ENABLED(CONFIG_ARCH_NPCM8XX)
903 int phy_uv;
904
905 phy_uv = dev_read_u32_default(dev, "phy-supply-microvolt", 0);
906 if (phy_uv) {
907 ret = regulator_set_value(phy_supply, phy_uv);
908 if (ret) {
909 puts("Error setting phy voltage\n");
910 return ret;
911 }
912 }
913 #endif
914 }
915 #endif
916
917 ret = reset_get_bulk(dev, &reset_bulk);
918 if (ret)
919 dev_warn(dev, "Can't get reset: %d\n", ret);
920 else
921 reset_deassert_bulk(&reset_bulk);
922
923 /*
924 * If we are on PCI bus, either directly attached to a PCI root port,
925 * or via a PCI bridge, fill in plat before we probe the hardware.
926 */
927 if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) {
928 u32 pcibase;
929
930 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase);
931 pcibase &= PCI_BASE_ADDRESS_MEM_MASK;
932
933 iobase = dm_pci_mem_to_phys(dev, pcibase);
934 pdata->iobase = iobase;
935 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
936 }
937
938 debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv);
939 ioaddr = phys_to_virt(iobase);
940 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
941 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
942 priv->interface = pdata->phy_interface;
943 priv->max_speed = pdata->max_speed;
944
945 #if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
946 if (dev_read_bool(dev, "snps,bitbang-mii")) {
947 ret = dw_bb_mdio_init(dev->name, dev);
948 if (ret) {
949 err = ret;
950 goto mdio_err;
951 }
952 } else
953 #endif
954 {
955 #if IS_ENABLED(CONFIG_DM_MDIO)
956 ret = dw_dm_mdio_init(dev->name, dev);
957 #else
958 ret = dw_mdio_init(dev->name, dev);
959 #endif
960 if (ret) {
961 err = ret;
962 goto mdio_err;
963 }
964 priv->bus = miiphy_get_dev_by_name(dev->name);
965 priv->dev = dev;
966 }
967
968 ret = dw_phy_init(priv, dev);
969 debug("%s, ret=%d\n", __func__, ret);
970 if (!ret)
971 return 0;
972
973 /* continue here for cleanup if no PHY found */
974 err = ret;
975 mdio_unregister(priv->bus);
976 mdio_free(priv->bus);
977 mdio_err:
978
979 #ifdef CONFIG_CLK
980 clk_err:
981 ret = clk_release_all(priv->clocks, priv->clock_count);
982 if (ret)
983 pr_err("failed to disable all clocks\n");
984
985 #endif
986 return err;
987 }
988
designware_eth_remove(struct udevice * dev)989 static int designware_eth_remove(struct udevice *dev)
990 {
991 struct dw_eth_dev *priv = dev_get_priv(dev);
992
993 free(priv->phydev);
994 mdio_unregister(priv->bus);
995 mdio_free(priv->bus);
996
997 #ifdef CONFIG_CLK
998 return clk_release_all(priv->clocks, priv->clock_count);
999 #else
1000 return 0;
1001 #endif
1002 }
1003
1004 const struct eth_ops designware_eth_ops = {
1005 .start = designware_eth_start,
1006 .send = designware_eth_send,
1007 .recv = designware_eth_recv,
1008 .free_pkt = designware_eth_free_pkt,
1009 .stop = designware_eth_stop,
1010 .write_hwaddr = designware_eth_write_hwaddr,
1011 };
1012
designware_eth_of_to_plat(struct udevice * dev)1013 int designware_eth_of_to_plat(struct udevice *dev)
1014 {
1015 struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
1016 #if CONFIG_IS_ENABLED(DM_GPIO)
1017 struct dw_eth_dev *priv = dev_get_priv(dev);
1018 #endif
1019 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
1020 #if CONFIG_IS_ENABLED(DM_GPIO)
1021 int reset_flags = GPIOD_IS_OUT;
1022 #endif
1023 int ret = 0;
1024
1025 pdata->iobase = dev_read_addr(dev);
1026 pdata->phy_interface = dev_read_phy_mode(dev);
1027 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1028 return -EINVAL;
1029
1030 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1031
1032 #if CONFIG_IS_ENABLED(DM_GPIO)
1033 if (dev_read_bool(dev, "snps,reset-active-low"))
1034 reset_flags |= GPIOD_ACTIVE_LOW;
1035
1036 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1037 &priv->reset_gpio, reset_flags);
1038 if (ret == 0) {
1039 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
1040 dw_pdata->reset_delays, 3);
1041 } else if (ret == -ENOENT) {
1042 ret = 0;
1043 }
1044 #endif
1045
1046 return ret;
1047 }
1048
1049 static const struct udevice_id designware_eth_ids[] = {
1050 { .compatible = "allwinner,sun7i-a20-gmac" },
1051 { .compatible = "amlogic,meson6-dwmac" },
1052 { .compatible = "st,stm32-dwmac" },
1053 { .compatible = "snps,arc-dwmac-3.70a" },
1054 { .compatible = "sophgo,cv1800b-dwmac" },
1055 { }
1056 };
1057
1058 U_BOOT_DRIVER(eth_designware) = {
1059 .name = "eth_designware",
1060 .id = UCLASS_ETH,
1061 .of_match = designware_eth_ids,
1062 .of_to_plat = designware_eth_of_to_plat,
1063 .bind = designware_eth_bind,
1064 .probe = designware_eth_probe,
1065 .remove = designware_eth_remove,
1066 .ops = &designware_eth_ops,
1067 .priv_auto = sizeof(struct dw_eth_dev),
1068 .plat_auto = sizeof(struct dw_eth_pdata),
1069 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1070 };
1071
1072 static struct pci_device_id supported[] = {
1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
1074 { }
1075 };
1076
1077 U_BOOT_PCI_DEVICE(eth_designware, supported);
1078