1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2023 Intel Coporation. 4 */ 5 6 #include <phy_interface.h> 7 #include <linux/bitops.h> 8 9 /* Core registers */ 10 11 #define XGMAC_MAC_REGS_BASE 0x000 12 13 struct xgmac_mac_regs { 14 u32 tx_configuration; /* 0x000 */ 15 u32 rx_configuration; /* 0x004 */ 16 u32 mac_packet_filter; /* 0x008 */ 17 u32 unused_00c[(0x070 - 0x00c) / 4]; /* 0x00c */ 18 u32 q0_tx_flow_ctrl; /* 0x070 */ 19 u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ 20 u32 rx_flow_ctrl; /* 0x090 */ 21 u32 unused_094[(0x0a0 - 0x094) / 4]; /* 0x094 */ 22 u32 rxq_ctrl0; /* 0x0a0 */ 23 u32 rxq_ctrl1; /* 0x0a4 */ 24 u32 rxq_ctrl2; /* 0x0a8 */ 25 u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ 26 u32 us_tic_counter; /* 0x0dc */ 27 u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ 28 u32 hw_feature0; /* 0x11c */ 29 u32 hw_feature1; /* 0x120 */ 30 u32 hw_feature2; /* 0x124 */ 31 u32 hw_feature3; /* 0x128 */ 32 u32 hw_feature4; /* 0x12c */ 33 u32 unused_130[(0x140 - 0x130) / 4]; /* 0x130 */ 34 u32 mac_extended_conf; /* 0x140 */ 35 u32 unused_144[(0x200 - 0x144) / 4]; /* 0x144 */ 36 u32 mdio_address; /* 0x200 */ 37 u32 mdio_data; /* 0x204 */ 38 u32 mdio_cont_write_addr; /* 0x208 */ 39 u32 mdio_cont_write_data; /* 0x20c */ 40 u32 mdio_cont_scan_port_enable; /* 0x210 */ 41 u32 mdio_intr_status; /* 0x214 */ 42 u32 mdio_intr_enable; /* 0x218 */ 43 u32 mdio_port_cnct_dsnct_status; /* 0x21c */ 44 u32 mdio_clause_22_port; /* 0x220 */ 45 u32 unused_224[(0x300 - 0x224) / 4]; /* 0x224 */ 46 u32 address0_high; /* 0x300 */ 47 u32 address0_low; /* 0x304 */ 48 }; 49 50 #define XGMAC_TIMEOUT_100MS 100000 51 #define XGMAC_MAC_CONF_SS_SHIFT 29 52 #define XGMAC_MAC_CONF_SS_10G_XGMII 0 53 #define XGMAC_MAC_CONF_SS_2_5G_GMII 2 54 #define XGMAC_MAC_CONF_SS_1G_GMII 3 55 #define XGMAC_MAC_CONF_SS_100M_MII 4 56 #define XGMAC_MAC_CONF_SS_5G_XGMII 5 57 #define XGMAC_MAC_CONF_SS_2_5G_XGMII 6 58 #define XGMAC_MAC_CONF_SS_2_10M_MII 7 59 60 #define XGMAC_MAC_CONF_JD BIT(16) 61 #define XGMAC_MAC_CONF_JE BIT(8) 62 #define XGMAC_MAC_CONF_WD BIT(7) 63 #define XGMAC_MAC_CONF_GPSLCE BIT(6) 64 #define XGMAC_MAC_CONF_CST BIT(2) 65 #define XGMAC_MAC_CONF_ACS BIT(1) 66 #define XGMAC_MAC_CONF_TE BIT(0) 67 #define XGMAC_MAC_CONF_RE BIT(0) 68 69 #define XGMAC_MAC_EXT_CONF_HD BIT(24) 70 71 #define XGMAC_MAC_PACKET_FILTER_RA BIT(31) 72 #define XGMAC_MAC_PACKET_FILTER_PR BIT(0) 73 74 #define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 75 #define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK GENMASK(15, 0) 76 #define XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) 77 78 #define XGMAC_MAC_RX_FLOW_CTRL_RFE BIT(0) 79 #define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 80 #define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK GENMASK(1, 0) 81 #define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 82 #define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 83 #define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 84 85 #define XGMAC_MAC_RXQ_CTRL1_MCBCQEN BIT(15) 86 87 #define XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 88 #define XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK GENMASK(7, 0) 89 90 #define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 91 #define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK GENMASK(4, 0) 92 #define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 93 #define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK GENMASK(4, 0) 94 95 #define XGMAC_MDIO_SINGLE_CMD_SHIFT 16 96 #define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ 3 << XGMAC_MDIO_SINGLE_CMD_SHIFT 97 #define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE BIT(16) 98 #define XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT 16 99 #define XGMAC_MAC_MDIO_ADDRESS_PA_MASK GENMASK(15, 0) 100 #define XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT 21 101 #define XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT 19 102 #define XGMAC_MAC_MDIO_ADDRESS_CR_100_150 0 103 #define XGMAC_MAC_MDIO_ADDRESS_CR_150_250 1 104 #define XGMAC_MAC_MDIO_ADDRESS_CR_250_300 2 105 #define XGMAC_MAC_MDIO_ADDRESS_CR_300_350 3 106 #define XGMAC_MAC_MDIO_ADDRESS_CR_350_400 4 107 #define XGMAC_MAC_MDIO_ADDRESS_CR_400_500 5 108 #define XGMAC_MAC_MDIO_ADDRESS_SADDR BIT(18) 109 #define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22) 110 #define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0) 111 #define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0) 112 113 /* MTL Registers */ 114 115 #define XGMAC_MTL_REGS_BASE 0x1000 116 117 struct xgmac_mtl_regs { 118 u32 mtl_operation_mode; /* 0x1000 */ 119 u32 unused_1004[(0x1030 - 0x1004) / 4]; /* 0x1004 */ 120 u32 mtl_rxq_dma_map0; /* 0x1030 */ 121 u32 mtl_rxq_dma_map1; /* 0x1034 */ 122 u32 mtl_rxq_dma_map2; /* 0x1038 */ 123 u32 mtl_rxq_dma_map3; /* 0x103c */ 124 u32 mtl_tc_prty_map0; /* 0x1040 */ 125 u32 mtl_tc_prty_map1; /* 0x1044 */ 126 u32 unused_1048[(0x1100 - 0x1048) / 4]; /* 0x1048 */ 127 u32 txq0_operation_mode; /* 0x1100 */ 128 u32 unused_1104; /* 0x1104 */ 129 u32 txq0_debug; /* 0x1108 */ 130 u32 unused_100c[(0x1118 - 0x110c) / 4]; /* 0x110c */ 131 u32 txq0_quantum_weight; /* 0x1118 */ 132 u32 unused_111c[(0x1140 - 0x111c) / 4]; /* 0x111c */ 133 u32 rxq0_operation_mode; /* 0x1140 */ 134 u32 unused_1144; /* 0x1144 */ 135 u32 rxq0_debug; /* 0x1148 */ 136 }; 137 138 #define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 139 #define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK GENMASK(8, 0) 140 #define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 141 #define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 142 #define XGMAC_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) 143 #define XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) 144 145 #define XGMAC_MTL_TXQ0_DEBUG_TXQSTS BIT(4) 146 #define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 147 #define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK GENMASK(2, 0) 148 #define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE 0x1 149 150 #define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 16 151 #define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK GENMASK(9, 0) 152 #define XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) 153 #define XGMAC_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) 154 155 #define XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 156 #define XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK GENMASK(14, 0) 157 #define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 158 #define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK GENMASK(1, 0) 159 160 /* DMA Registers */ 161 162 #define XGMAC_DMA_REGS_BASE 0x3000 163 164 struct xgmac_dma_regs { 165 u32 mode; /* 0x3000 */ 166 u32 sysbus_mode; /* 0x3004 */ 167 u32 unused_3008[(0x3100 - 0x3008) / 4]; /* 0x3008 */ 168 u32 ch0_control; /* 0x3100 */ 169 u32 ch0_tx_control; /* 0x3104 */ 170 u32 ch0_rx_control; /* 0x3108 */ 171 u32 slot_func_control_status; /* 0x310c */ 172 u32 ch0_txdesc_list_haddress; /* 0x3110 */ 173 u32 ch0_txdesc_list_address; /* 0x3114 */ 174 u32 ch0_rxdesc_list_haddress; /* 0x3118 */ 175 u32 ch0_rxdesc_list_address; /* 0x311c */ 176 u32 unused_3120; /* 0x3120 */ 177 u32 ch0_txdesc_tail_pointer; /* 0x3124 */ 178 u32 unused_3128; /* 0x3128 */ 179 u32 ch0_rxdesc_tail_pointer; /* 0x312c */ 180 u32 ch0_txdesc_ring_length; /* 0x3130 */ 181 u32 ch0_rxdesc_ring_length; /* 0x3134 */ 182 u32 unused_3138[(0x3160 - 0x3138) / 4]; /* 0x3138 */ 183 u32 ch0_status; /* 0x3160 */ 184 }; 185 186 #define XGMAC_DMA_MODE_SWR BIT(0) 187 #define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 188 #define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK GENMASK(4, 0) 189 #define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 190 #define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK GENMASK(4, 0) 191 #define XGMAC_DMA_SYSBUS_MODE_AAL BIT(12) 192 #define XGMAC_DMA_SYSBUS_MODE_EAME BIT(11) 193 #define XGMAC_DMA_SYSBUS_MODE_BLEN32 BIT(4) 194 #define XGMAC_DMA_SYSBUS_MODE_BLEN16 BIT(3) 195 #define XGMAC_DMA_SYSBUS_MODE_BLEN8 BIT(2) 196 #define XGMAC_DMA_SYSBUS_MODE_BLEN4 BIT(1) 197 #define XGMAC_DMA_SYSBUS_MODE_UNDEF BIT(0) 198 199 #define XGMAC_DMA_CH0_CONTROL_DSL_SHIFT 18 200 #define XGMAC_DMA_CH0_CONTROL_PBLX8 BIT(16) 201 202 #define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 203 #define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK GENMASK(5, 0) 204 #define XGMAC_DMA_CH0_TX_CONTROL_OSP BIT(4) 205 #define XGMAC_DMA_CH0_TX_CONTROL_ST BIT(0) 206 207 #define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 208 #define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK GENMASK(5, 0) 209 #define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 4 210 #define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK GENMASK(10, 0) 211 #define XGMAC_DMA_CH0_RX_CONTROL_SR BIT(0) 212 213 /* Descriptors */ 214 #define XGMAC_DESCRIPTORS_TX 8 215 #define XGMAC_DESCRIPTORS_RX 8 216 #define XGMAC_BUFFER_ALIGN ARCH_DMA_MINALIGN 217 #define XGMAC_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) 218 #define XGMAC_RX_BUFFER_SIZE (XGMAC_DESCRIPTORS_RX * XGMAC_MAX_PACKET_SIZE) 219 220 #define XGMAC_RDES3_PKT_LENGTH_MASK GENMASK(13, 0) 221 222 struct xgmac_desc { 223 u32 des0; 224 u32 des1; 225 u32 des2; 226 u32 des3; 227 }; 228 229 #define XGMAC_DESC3_OWN BIT(31) 230 #define XGMAC_DESC3_FD BIT(29) 231 #define XGMAC_DESC3_LD BIT(28) 232 233 #define XGMAC_AXI_WIDTH_32 4 234 #define XGMAC_AXI_WIDTH_64 8 235 #define XGMAC_AXI_WIDTH_128 16 236 237 struct xgmac_config { 238 bool reg_access_always_ok; 239 int swr_wait; 240 int config_mac; 241 int config_mac_mdio; 242 unsigned int axi_bus_width; 243 phy_interface_t (*interface)(const struct udevice *dev); 244 struct xgmac_ops *ops; 245 }; 246 247 struct xgmac_ops { 248 void (*xgmac_inval_desc)(void *desc); 249 void (*xgmac_flush_desc)(void *desc); 250 void (*xgmac_inval_buffer)(void *buf, size_t size); 251 void (*xgmac_flush_buffer)(void *buf, size_t size); 252 int (*xgmac_probe_resources)(struct udevice *dev); 253 int (*xgmac_remove_resources)(struct udevice *dev); 254 int (*xgmac_stop_resets)(struct udevice *dev); 255 int (*xgmac_start_resets)(struct udevice *dev); 256 int (*xgmac_stop_clks)(struct udevice *dev); 257 int (*xgmac_start_clks)(struct udevice *dev); 258 int (*xgmac_calibrate_pads)(struct udevice *dev); 259 int (*xgmac_disable_calibration)(struct udevice *dev); 260 int (*xgmac_get_enetaddr)(struct udevice *dev); 261 }; 262 263 struct xgmac_priv { 264 struct udevice *dev; 265 const struct xgmac_config *config; 266 fdt_addr_t regs; 267 struct xgmac_mac_regs *mac_regs; 268 struct xgmac_mtl_regs *mtl_regs; 269 struct xgmac_dma_regs *dma_regs; 270 struct reset_ctl reset_ctl; 271 struct reset_ctl_bulk reset_bulk; 272 struct clk clk_common; 273 struct mii_dev *mii; 274 struct phy_device *phy; 275 ofnode phy_of_node; 276 void *syscon_phy; 277 u32 syscon_phy_regshift; 278 u32 max_speed; 279 void *tx_descs; 280 void *rx_descs; 281 int tx_desc_idx, rx_desc_idx; 282 unsigned int desc_size; 283 unsigned int desc_per_cacheline; 284 void *tx_dma_buf; 285 void *rx_dma_buf; 286 void *rx_pkt; 287 bool started; 288 bool reg_access_ok; 289 bool clk_ck_enabled; 290 }; 291 292 void xgmac_inval_desc_generic(void *desc); 293 void xgmac_flush_desc_generic(void *desc); 294 void xgmac_inval_buffer_generic(void *buf, size_t size); 295 void xgmac_flush_buffer_generic(void *buf, size_t size); 296 int xgmac_null_ops(struct udevice *dev); 297 298 extern struct xgmac_config xgmac_socfpga_config; 299