1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
4 *
5 * Altera SoCFPGA EMAC extras
6 */
7
8 #include <asm/arch/secure_reg_helper.h>
9 #include <asm/arch/system_manager.h>
10 #include <asm/io.h>
11 #include <dm.h>
12 #include <clk.h>
13 #include <phy.h>
14 #include <regmap.h>
15 #include <reset.h>
16 #include <syscon.h>
17 #include "designware.h"
18 #include <dm/device_compat.h>
19 #include <linux/err.h>
20
21 struct dwmac_socfpga_plat {
22 struct dw_eth_pdata dw_eth_pdata;
23 void *phy_intf;
24 u32 reg_shift;
25 };
26
dwmac_socfpga_of_to_plat(struct udevice * dev)27 static int dwmac_socfpga_of_to_plat(struct udevice *dev)
28 {
29 struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
30 struct regmap *regmap;
31 struct ofnode_phandle_args args;
32 void *range;
33 int ret;
34
35 ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
36 2, 0, &args);
37 if (ret) {
38 dev_err(dev, "Failed to get syscon: %d\n", ret);
39 return ret;
40 }
41
42 if (args.args_count != 2) {
43 dev_err(dev, "Invalid number of syscon args\n");
44 return -EINVAL;
45 }
46
47 regmap = syscon_node_to_regmap(args.node);
48 if (IS_ERR(regmap)) {
49 ret = PTR_ERR(regmap);
50 dev_err(dev, "Failed to get regmap: %d\n", ret);
51 return ret;
52 }
53
54 range = regmap_get_range(regmap, 0);
55 if (!range) {
56 dev_err(dev, "Failed to get regmap range\n");
57 return -ENOMEM;
58 }
59
60 pdata->phy_intf = range + args.args[0];
61 pdata->reg_shift = args.args[1];
62
63 return designware_eth_of_to_plat(dev);
64 }
65
dwmac_socfpga_do_setphy(struct udevice * dev,u32 modereg)66 static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
67 {
68 struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
69 u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
70
71 #if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
72 u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
73 SYSMGR_SOC64_EMAC0) >> 2;
74
75 u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
76
77 int ret = socfpga_secure_reg_update32(id,
78 modemask,
79 modereg << pdata->reg_shift);
80 if (ret) {
81 dev_err(dev, "Failed to set PHY register via SMC call\n");
82 return ret;
83 }
84 #else
85 clrsetbits_le32(pdata->phy_intf, modemask,
86 modereg << pdata->reg_shift);
87 #endif
88
89 return 0;
90 }
91
dwmac_socfpga_probe(struct udevice * dev)92 static int dwmac_socfpga_probe(struct udevice *dev)
93 {
94 struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
95 struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
96 struct reset_ctl_bulk reset_bulk;
97 int ret;
98 u32 modereg;
99
100 switch (edata->phy_interface) {
101 case PHY_INTERFACE_MODE_MII:
102 case PHY_INTERFACE_MODE_GMII:
103 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
104 break;
105 case PHY_INTERFACE_MODE_RMII:
106 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
107 break;
108 case PHY_INTERFACE_MODE_RGMII:
109 case PHY_INTERFACE_MODE_RGMII_ID:
110 case PHY_INTERFACE_MODE_RGMII_RXID:
111 case PHY_INTERFACE_MODE_RGMII_TXID:
112 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
113 break;
114 default:
115 dev_err(dev, "Unsupported PHY mode\n");
116 return -EINVAL;
117 }
118
119 ret = reset_get_bulk(dev, &reset_bulk);
120 if (ret) {
121 dev_err(dev, "Failed to get reset: %d\n", ret);
122 return ret;
123 }
124
125 reset_assert_bulk(&reset_bulk);
126
127 ret = dwmac_socfpga_do_setphy(dev, modereg);
128 if (ret)
129 return ret;
130
131 reset_release_bulk(&reset_bulk);
132
133 return designware_eth_probe(dev);
134 }
135
136 static const struct udevice_id dwmac_socfpga_ids[] = {
137 { .compatible = "altr,socfpga-stmmac" },
138 { }
139 };
140
141 U_BOOT_DRIVER(dwmac_socfpga) = {
142 .name = "dwmac_socfpga",
143 .id = UCLASS_ETH,
144 .of_match = dwmac_socfpga_ids,
145 .of_to_plat = dwmac_socfpga_of_to_plat,
146 .probe = dwmac_socfpga_probe,
147 .ops = &designware_eth_ops,
148 .priv_auto = sizeof(struct dw_eth_dev),
149 .plat_auto = sizeof(struct dwmac_socfpga_plat),
150 .flags = DM_FLAG_ALLOC_PRIV_DMA,
151 };
152