1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Faraday FTGMAC100 Ethernet 4 * 5 * (C) Copyright 2010 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 * 8 * (C) Copyright 2010 Andes Technology 9 * Macpaul Lin <macpaul@andestech.com> 10 */ 11 12 #ifndef __FTGMAC100_H 13 #define __FTGMAC100_H 14 15 /* The registers offset table of ftgmac100 */ 16 #include <linux/bitops.h> 17 struct ftgmac100 { 18 unsigned int isr; /* 0x00 */ 19 unsigned int ier; /* 0x04 */ 20 unsigned int mac_madr; /* 0x08 */ 21 unsigned int mac_ladr; /* 0x0c */ 22 unsigned int maht0; /* 0x10 */ 23 unsigned int maht1; /* 0x14 */ 24 unsigned int txpd; /* 0x18 */ 25 unsigned int rxpd; /* 0x1c */ 26 unsigned int txr_badr; /* 0x20 */ 27 unsigned int rxr_badr; /* 0x24 */ 28 unsigned int hptxpd; /* 0x28 */ 29 unsigned int hptxpd_badr; /* 0x2c */ 30 unsigned int itc; /* 0x30 */ 31 unsigned int aptc; /* 0x34 */ 32 unsigned int dblac; /* 0x38 */ 33 unsigned int dmafifos; /* 0x3c */ 34 unsigned int revr; /* 0x40 */ 35 unsigned int fear; /* 0x44 */ 36 unsigned int tpafcr; /* 0x48 */ 37 unsigned int rbsr; /* 0x4c */ 38 unsigned int maccr; /* 0x50 */ 39 unsigned int macsr; /* 0x54 */ 40 unsigned int tm; /* 0x58 */ 41 unsigned int resv1; /* 0x5c */ /* not defined in spec */ 42 unsigned int phycr; /* 0x60 */ 43 unsigned int phydata; /* 0x64 */ 44 unsigned int fcr; /* 0x68 */ 45 unsigned int bpr; /* 0x6c */ 46 unsigned int wolcr; /* 0x70 */ 47 unsigned int wolsr; /* 0x74 */ 48 unsigned int wfcrc; /* 0x78 */ 49 unsigned int resv2; /* 0x7c */ /* not defined in spec */ 50 unsigned int wfbm1; /* 0x80 */ 51 unsigned int wfbm2; /* 0x84 */ 52 unsigned int wfbm3; /* 0x88 */ 53 unsigned int wfbm4; /* 0x8c */ 54 unsigned int nptxr_ptr; /* 0x90 */ 55 unsigned int hptxr_ptr; /* 0x94 */ 56 unsigned int rxr_ptr; /* 0x98 */ 57 unsigned int resv3; /* 0x9c */ /* not defined in spec */ 58 unsigned int tx; /* 0xa0 */ 59 unsigned int tx_mcol_scol; /* 0xa4 */ 60 unsigned int tx_ecol_fail; /* 0xa8 */ 61 unsigned int tx_lcol_und; /* 0xac */ 62 unsigned int rx; /* 0xb0 */ 63 unsigned int rx_bc; /* 0xb4 */ 64 unsigned int rx_mc; /* 0xb8 */ 65 unsigned int rx_pf_aep; /* 0xbc */ 66 unsigned int rx_runt; /* 0xc0 */ 67 unsigned int rx_crcer_ftl; /* 0xc4 */ 68 unsigned int rx_col_lost; /* 0xc8 */ 69 unsigned int reserved[43]; /* 0xcc - 0x174 */ 70 unsigned int txr_badr_lo; /* 0x178, defined in ast2700 */ 71 unsigned int txr_badr_hi; /* 0x17c, defined in ast2700 */ 72 unsigned int hptxr_badr_lo; /* 0x180, defined in ast2700 */ 73 unsigned int hptxr_badr_hi; /* 0x184, defined in ast2700 */ 74 unsigned int rxr_badr_lo; /* 0x188, defined in ast2700 */ 75 unsigned int rxr_badr_hi; /* 0x18c, defined in ast2700 */ 76 }; 77 78 /* 79 * Interrupt status register & interrupt enable register 80 */ 81 #define FTGMAC100_INT_RPKT_BUF BIT(0) 82 #define FTGMAC100_INT_RPKT_FIFO BIT(1) 83 #define FTGMAC100_INT_NO_RXBUF BIT(2) 84 #define FTGMAC100_INT_RPKT_LOST BIT(3) 85 #define FTGMAC100_INT_XPKT_ETH BIT(4) 86 #define FTGMAC100_INT_XPKT_FIFO BIT(5) 87 #define FTGMAC100_INT_NO_NPTXBUF BIT(6) 88 #define FTGMAC100_INT_XPKT_LOST BIT(7) 89 #define FTGMAC100_INT_AHB_ERR BIT(8) 90 #define FTGMAC100_INT_PHYSTS_CHG BIT(9) 91 #define FTGMAC100_INT_NO_HPTXBUF BIT(10) 92 93 /* 94 * Interrupt timer control register 95 */ 96 #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) 97 #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) 98 #define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) 99 #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) 100 #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) 101 #define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15) 102 103 /* 104 * Automatic polling timer control register 105 */ 106 #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 107 #define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) 108 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 109 #define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12) 110 111 /* 112 * DMA burst length and arbitration control register 113 */ 114 #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) 115 #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) 116 #define FTGMAC100_DBLAC_RX_THR_EN BIT(6) 117 #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) 118 #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) 119 #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) 120 #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) 121 #define FTGMAC100_DESC_UNIT 8 122 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) 123 #define FTGMAC100_DBLAC_IFG_INC BIT(23) 124 125 /* 126 * DMA FIFO status register 127 */ 128 #define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) 129 #define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) 130 #define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) 131 #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) 132 #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) 133 #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) 134 #define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) 135 #define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) 136 #define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) 137 #define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) 138 #define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) 139 #define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31) 140 141 /* 142 * Receive buffer size register 143 */ 144 #define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) 145 146 /* 147 * MAC control register 148 */ 149 #define FTGMAC100_MACCR_TXDMA_EN BIT(0) 150 #define FTGMAC100_MACCR_RXDMA_EN BIT(1) 151 #define FTGMAC100_MACCR_TXMAC_EN BIT(2) 152 #define FTGMAC100_MACCR_RXMAC_EN BIT(3) 153 #define FTGMAC100_MACCR_RM_VLAN BIT(4) 154 #define FTGMAC100_MACCR_HPTXR_EN BIT(5) 155 #define FTGMAC100_MACCR_LOOP_EN BIT(6) 156 #define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) 157 #define FTGMAC100_MACCR_FULLDUP BIT(8) 158 #define FTGMAC100_MACCR_GIGA_MODE BIT(9) 159 #define FTGMAC100_MACCR_CRC_APD BIT(10) 160 #define FTGMAC100_MACCR_RX_RUNT BIT(12) 161 #define FTGMAC100_MACCR_JUMBO_LF BIT(13) 162 #define FTGMAC100_MACCR_RX_ALL BIT(14) 163 #define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) 164 #define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) 165 #define FTGMAC100_MACCR_RX_BROADPKT BIT(17) 166 #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) 167 #define FTGMAC100_MACCR_FAST_MODE BIT(19) 168 #define FTGMAC100_MACCR_RMII_ENABLE BIT(20) /* defined in ast2700 */ 169 #define FTGMAC100_MACCR_SW_RST BIT(31) 170 171 /* 172 * PHY control register 173 */ 174 #define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f 175 #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) 176 #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) 177 #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) 178 #define FTGMAC100_PHYCR_MIIRD BIT(26) 179 #define FTGMAC100_PHYCR_MIIWR BIT(27) 180 181 /* 182 * PHY data register 183 */ 184 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) 185 #define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) 186 187 /* 188 * Transmit descriptor, aligned to 16 bytes 189 */ 190 struct ftgmac100_txdes { 191 unsigned int txdes0; 192 unsigned int txdes1; 193 unsigned int txdes2; /* not used by HW */ 194 unsigned int txdes3; /* TXBUF_BADR */ 195 } __aligned(ARCH_DMA_MINALIGN); 196 197 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) 198 #define FTGMAC100_TXDES0_EDOTR BIT(15) 199 #define FTGMAC100_TXDES0_CRC_ERR BIT(19) 200 #define FTGMAC100_TXDES0_LTS BIT(28) 201 #define FTGMAC100_TXDES0_FTS BIT(29) 202 #define FTGMAC100_TXDES0_TXDMA_OWN BIT(31) 203 204 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) 205 #define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) 206 #define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) 207 #define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) 208 #define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) 209 #define FTGMAC100_TXDES1_LLC BIT(22) 210 #define FTGMAC100_TXDES1_TX2FIC BIT(30) 211 #define FTGMAC100_TXDES1_TXIC BIT(31) 212 213 #define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16) 214 215 /* 216 * Receive descriptor, aligned to 16 bytes 217 */ 218 struct ftgmac100_rxdes { 219 unsigned int rxdes0; 220 unsigned int rxdes1; 221 unsigned int rxdes2; /* not used by HW */ 222 unsigned int rxdes3; /* RXBUF_BADR */ 223 } __aligned(ARCH_DMA_MINALIGN); 224 225 #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) 226 #define FTGMAC100_RXDES0_EDORR BIT(15) 227 #define FTGMAC100_RXDES0_MULTICAST BIT(16) 228 #define FTGMAC100_RXDES0_BROADCAST BIT(17) 229 #define FTGMAC100_RXDES0_RX_ERR BIT(18) 230 #define FTGMAC100_RXDES0_CRC_ERR BIT(19) 231 #define FTGMAC100_RXDES0_FTL BIT(20) 232 #define FTGMAC100_RXDES0_RUNT BIT(21) 233 #define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) 234 #define FTGMAC100_RXDES0_FIFO_FULL BIT(23) 235 #define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) 236 #define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) 237 #define FTGMAC100_RXDES0_LRS BIT(28) 238 #define FTGMAC100_RXDES0_FRS BIT(29) 239 #define FTGMAC100_RXDES0_RXPKT_RDY BIT(31) 240 241 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff 242 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) 243 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) 244 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) 245 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) 246 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) 247 #define FTGMAC100_RXDES1_LLC BIT(22) 248 #define FTGMAC100_RXDES1_DF BIT(23) 249 #define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) 250 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) 251 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) 252 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) 253 254 #define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16) 255 256 #endif /* __FTGMAC100_H */ 257