1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 */
6
7 #include <config.h>
8 #include <net.h>
9 #include <netdev.h>
10 #include <asm/global_data.h>
11 #include <linux/delay.h>
12
13 #include <asm/fec.h>
14 #include <asm/immap.h>
15 #include <linux/mii.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #if defined(CONFIG_CMD_NET)
20 #undef MII_DEBUG
21 #undef ET_DEBUG
22
23 /*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
24
25 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
26 #include <miiphy.h>
27
28 /* Make MII read/write commands for the FEC. */
29 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
30 (REG & 0x1f) << 18))
31 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
32 (REG & 0x1f) << 18) | (VAL & 0xffff))
33
34 #ifndef CFG_SYS_UNSPEC_PHYID
35 # define CFG_SYS_UNSPEC_PHYID 0
36 #endif
37 #ifndef CFG_SYS_UNSPEC_STRID
38 # define CFG_SYS_UNSPEC_STRID 0
39 #endif
40
41 typedef struct phy_info_struct {
42 u32 phyid;
43 char *strid;
44 } phy_info_t;
45
46 phy_info_t phyinfo[] = {
47 {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
48 {0x00406322, "BCM5222"}, /* Broadcom 5222 */
49 {0x02a80150, "Intel82555"}, /* Intel 82555 */
50 {0x0016f870, "LSI80225"}, /* LSI 80225 */
51 {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */
52 {0x78100000, "LXT970"}, /* LXT970 */
53 {0x001378e0, "LXT971"}, /* LXT971 and 972 */
54 {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */
55 {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */
56 {0x20005CE1, "N83640"}, /* National 83640 */
57 {0x20005C90, "N83848"}, /* National 83848 */
58 {0x20005CA2, "N83849"}, /* National 83849 */
59 {0x01814400, "QS6612"}, /* QS6612 */
60 #if defined(CFG_SYS_UNSPEC_PHYID) && defined(CFG_SYS_UNSPEC_STRID)
61 {CFG_SYS_UNSPEC_PHYID, CFG_SYS_UNSPEC_STRID},
62 #endif
63 {0, 0}
64 };
65
66 /*
67 * mii_init -- Initialize the MII for MII command without ethernet
68 * This function is a subset of eth_init
69 */
mii_reset(fec_info_t * info)70 void mii_reset(fec_info_t *info)
71 {
72 volatile FEC_T *fecp = (FEC_T *) (info->miibase);
73 int i;
74
75 fecp->ecr = FEC_ECR_RESET;
76
77 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
78 udelay(1);
79 }
80 if (i == FEC_RESET_DELAY)
81 printf("FEC_RESET_DELAY timeout\n");
82 }
83
84 /* send command to phy using mii, wait for result */
mii_send(uint mii_cmd)85 uint mii_send(uint mii_cmd)
86 {
87 struct udevice *dev;
88 fec_info_t *info;
89 volatile FEC_T *ep;
90 uint mii_reply;
91 int j = 0;
92
93 /* retrieve from register structure */
94 dev = eth_get_dev();
95 info = dev_get_priv(dev);
96
97 ep = (FEC_T *) info->miibase;
98
99 ep->mmfr = mii_cmd; /* command to phy */
100
101 /* wait for mii complete */
102 while (!(ep->eir & FEC_EIR_MII) && (j < info->to_loop)) {
103 udelay(1);
104 j++;
105 }
106 if (j >= info->to_loop) {
107 printf("MII not complete\n");
108 return -1;
109 }
110
111 mii_reply = ep->mmfr; /* result from phy */
112 ep->eir = FEC_EIR_MII; /* clear MII complete */
113 #ifdef ET_DEBUG
114 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
115 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
116 #endif
117
118 return (mii_reply & 0xffff); /* data read from phy */
119 }
120 #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
121
122 #if defined(CONFIG_SYS_DISCOVER_PHY)
mii_discover_phy(fec_info_t * info)123 int mii_discover_phy(fec_info_t *info)
124 {
125 #define MAX_PHY_PASSES 11
126 int phyaddr, pass;
127 uint phyno, phytype;
128 int i, found = 0;
129
130 if (info->phyname_init)
131 return info->phy_addr;
132
133 phyaddr = -1; /* didn't find a PHY yet */
134 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
135 if (pass > 1) {
136 /* PHY may need more time to recover from reset.
137 * The LXT970 needs 50ms typical, no maximum is
138 * specified, so wait 10ms before try again.
139 * With 11 passes this gives it 100ms to wake up.
140 */
141 udelay(10000); /* wait 10ms */
142 }
143
144 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
145
146 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
147 #ifdef ET_DEBUG
148 printf("PHY type 0x%x pass %d\n", phytype, pass);
149 #endif
150 if (phytype == 0xffff)
151 continue;
152 phyaddr = phyno;
153 phytype <<= 16;
154 phytype |=
155 mii_send(mk_mii_read(phyno, MII_PHYSID2));
156
157 #ifdef ET_DEBUG
158 printf("PHY @ 0x%x pass %d\n", phyno, pass);
159 #endif
160
161 for (i = 0; (i < ARRAY_SIZE(phyinfo))
162 && (phyinfo[i].phyid != 0); i++) {
163 if (phyinfo[i].phyid == phytype) {
164 #ifdef ET_DEBUG
165 printf("phyid %x - %s\n",
166 phyinfo[i].phyid,
167 phyinfo[i].strid);
168 #endif
169 strcpy(info->phy_name, phyinfo[i].strid);
170 info->phyname_init = 1;
171 found = 1;
172 break;
173 }
174 }
175
176 if (!found) {
177 #ifdef ET_DEBUG
178 printf("0x%08x\n", phytype);
179 #endif
180 strcpy(info->phy_name, "unknown");
181 info->phyname_init = 1;
182 break;
183 }
184 }
185 }
186
187 if (phyaddr < 0)
188 printf("No PHY device found.\n");
189
190 return phyaddr;
191 }
192 #endif /* CONFIG_SYS_DISCOVER_PHY */
193
mii_init(void)194 __weak void mii_init(void)
195 {
196 struct udevice *dev;
197 fec_info_t *info;
198 volatile FEC_T *fecp;
199 int miispd = 0, i = 0;
200 u16 status = 0;
201 u16 linkgood = 0;
202
203 /* retrieve from register structure */
204 dev = eth_get_dev();
205 info = dev_get_priv(dev);
206
207 fecp = (FEC_T *) info->miibase;
208
209 fecpin_setclear(info, 1);
210
211 mii_reset(info);
212
213 /* We use strictly polling mode only */
214 fecp->eimr = 0;
215
216 /* Clear any pending interrupt */
217 fecp->eir = 0xffffffff;
218
219 /* Set MII speed */
220 miispd = (gd->bus_clk / 1000000) / 5;
221 fecp->mscr = miispd << 1;
222
223 #ifdef CONFIG_SYS_DISCOVER_PHY
224 info->phy_addr = mii_discover_phy(info);
225 #endif
226 if (info->phy_addr == -1)
227 return;
228
229 while (i < info->to_loop) {
230 status = 0;
231 i++;
232 /* Read PHY control register */
233 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
234
235 /* If phy set to autonegotiate, wait for autonegotiation done,
236 * if phy is not autonegotiating, just wait for link up.
237 */
238 if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
239 linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
240 } else {
241 linkgood = BMSR_LSTATUS;
242 }
243 /* Read PHY status register */
244 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
245 if ((status & linkgood) == linkgood)
246 break;
247
248 udelay(1);
249 }
250 if (i >= info->to_loop)
251 printf("Link UP timeout\n");
252
253 /* adapt to the duplex and speed settings of the phy */
254 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
255 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
256 }
257
258 /*
259 * Read and write a MII PHY register, routines used by MII Utilities
260 *
261 * FIXME: These routines are expected to return 0 on success, but mii_send
262 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
263 * no PHY connected...
264 * For now always return 0.
265 * FIXME: These routines only work after calling eth_init() at least once!
266 * Otherwise they hang in mii_send() !!! Sorry!
267 */
268
mcffec_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)269 int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
270 {
271 short rdreg; /* register working value */
272
273 #ifdef MII_DEBUG
274 printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
275 #endif
276 rdreg = mii_send(mk_mii_read(addr, reg));
277
278 #ifdef MII_DEBUG
279 printf("0x%04x\n", rdreg);
280 #endif
281
282 return rdreg;
283 }
284
mcffec_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)285 int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
286 u16 value)
287 {
288 #ifdef MII_DEBUG
289 printf("miiphy_write(0x%x) @ 0x%x = 0x%04x\n", reg, addr, value);
290 #endif
291
292 mii_send(mk_mii_write(addr, reg, value));
293
294 return 0;
295 }
296
297 #endif /* CONFIG_CMD_NET */
298