1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Felix (VSC9959) Ethernet switch driver
4 * Copyright 2018-2021 NXP
5 */
6
7 /*
8 * This driver is used for the Ethernet switch integrated into NXP LS1028A.
9 * Felix switch is derived from Microsemi Ocelot but there are several NXP
10 * adaptations that makes the two U-Boot drivers largely incompatible.
11 *
12 * Felix on LS1028A has 4 front panel ports and two internal ports, connected
13 * to ENETC interfaces. We're using one of the ENETC interfaces to push traffic
14 * into the switch. Injection/extraction headers are used to identify
15 * egress/ingress ports in the switch for Tx/Rx.
16 */
17
18 #include <dm/device_compat.h>
19 #include <dm/of_extra.h>
20 #include <linux/delay.h>
21 #include <net/dsa.h>
22 #include <asm/io.h>
23 #include <miiphy.h>
24 #include <pci.h>
25
26 /* defines especially around PCS are reused from enetc */
27 #include "../fsl_enetc.h"
28
29 #define PCI_DEVICE_ID_FELIX_ETHSW 0xEEF0
30
31 /* Felix has in fact 6 ports, but we don't use the last internal one */
32 #define FELIX_PORT_COUNT 5
33 /* Front panel port mask */
34 #define FELIX_FP_PORT_MASK 0xf
35
36 /* Register map for BAR4 */
37 #define FELIX_SYS 0x010000
38 #define FELIX_ES0 0x040000
39 #define FELIX_IS1 0x050000
40 #define FELIX_IS2 0x060000
41 #define FELIX_GMII(port) (0x100000 + (port) * 0x10000)
42 #define FELIX_QSYS 0x200000
43 #define FELIX_DEVCPU_GCB 0x070000
44 #define FELIX_DEVCPU_GCB_SOFT_RST (FELIX_DEVCPU_GCB + 0x00000004)
45 #define SOFT_SWC_RST BIT(0)
46 #define FELIX_SYS_SYSTEM (FELIX_SYS + 0x00000E00)
47 #define FELIX_SYS_SYSTEM_EN BIT(0)
48 #define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x00000F24)
49 #define FELIX_SYS_RAM_CTRL_INIT BIT(1)
50 #define FELIX_SYS_SYSTEM_PORT_MODE(a) (FELIX_SYS_SYSTEM + 0xC + (a) * 4)
51 #define FELIX_SYS_SYSTEM_PORT_MODE_CPU 0x0000001e
52
53 #define FELIX_ES0_TCAM_CTRL (FELIX_ES0 + 0x000003C0)
54 #define FELIX_ES0_TCAM_CTRL_EN BIT(0)
55 #define FELIX_IS1_TCAM_CTRL (FELIX_IS1 + 0x000003C0)
56 #define FELIX_IS1_TCAM_CTRL_EN BIT(0)
57 #define FELIX_IS2_TCAM_CTRL (FELIX_IS2 + 0x000003C0)
58 #define FELIX_IS2_TCAM_CTRL_EN BIT(0)
59
60 #define FELIX_GMII_CLOCK_CFG(port) (FELIX_GMII(port) + 0x00000000)
61 #define FELIX_GMII_CLOCK_CFG_LINK_1G 1
62 #define FELIX_GMII_CLOCK_CFG_LINK_100M 2
63 #define FELIX_GMII_CLOCK_CFG_LINK_10M 3
64 #define FELIX_GMII_MAC_ENA_CFG(port) (FELIX_GMII(port) + 0x0000001C)
65 #define FELIX_GMII_MAX_ENA_CFG_TX BIT(0)
66 #define FELIX_GMII_MAX_ENA_CFG_RX BIT(4)
67 #define FELIX_GMII_MAC_IFG_CFG(port) (FELIX_GMII(port) + 0x0000001C + 0x14)
68 #define FELIX_GMII_MAC_IFG_CFG_DEF 0x515
69
70 #define FELIX_QSYS_SYSTEM (FELIX_QSYS + 0x0000F460)
71 #define FELIX_QSYS_SYSTEM_SW_PORT_MODE(a) \
72 (FELIX_QSYS_SYSTEM + 0x20 + (a) * 4)
73 #define FELIX_QSYS_SYSTEM_SW_PORT_ENA BIT(14)
74 #define FELIX_QSYS_SYSTEM_SW_PORT_LOSSY BIT(9)
75 #define FELIX_QSYS_SYSTEM_SW_PORT_SCH(a) (((a) & 0x3800) << 11)
76 #define FELIX_QSYS_SYSTEM_EXT_CPU_CFG (FELIX_QSYS_SYSTEM + 0x80)
77 #define FELIX_QSYS_SYSTEM_EXT_CPU_PORT(a) (((a) & 0xf) << 8 | 0xff)
78
79 /* internal MDIO in BAR0 */
80 #define FELIX_PM_IMDIO_BASE 0x8030
81
82 /* Serdes block on LS1028A */
83 #define FELIX_SERDES_BASE 0x1ea0000L
84 #define FELIX_SERDES_LNATECR0(lane) (FELIX_SERDES_BASE + 0x818 + \
85 (lane) * 0x40)
86 #define FELIX_SERDES_LNATECR0_ADPT_EQ 0x00003000
87 #define FELIX_SERDES_SGMIICR1(lane) (FELIX_SERDES_BASE + 0x1804 + \
88 (lane) * 0x10)
89 #define FELIX_SERDES_SGMIICR1_SGPCS BIT(11)
90 #define FELIX_SERDES_SGMIICR1_MDEV(a) (((a) & 0x1f) << 27)
91
92 #define FELIX_PCS_CTRL 0
93 #define FELIX_PCS_CTRL_RST BIT(15)
94
95 /*
96 * The long prefix format used here contains two dummy MAC addresses, a magic
97 * value in place of a VLAN tag followed by the extraction/injection header and
98 * the original L2 frame. Out of all this we only use the port ID.
99 */
100 #define FELIX_DSA_TAG_LEN sizeof(struct felix_dsa_tag)
101 #define FELIX_DSA_TAG_MAGIC 0x0a008088
102 #define FELIX_DSA_TAG_INJ_PORT 7
103 #define FELIX_DSA_TAG_INJ_PORT_SET(a) (0x1 << ((a) & FELIX_FP_PORT_MASK))
104 #define FELIX_DSA_TAG_EXT_PORT 10
105 #define FELIX_DSA_TAG_EXT_PORT_GET(a) ((a) >> 3)
106
107 struct felix_dsa_tag {
108 uchar d_mac[6];
109 uchar s_mac[6];
110 u32 magic;
111 uchar meta[16];
112 };
113
114 struct felix_priv {
115 void *regs_base;
116 void *imdio_base;
117 struct mii_dev imdio;
118 };
119
120 /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
felix_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)121 static int felix_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
122 {
123 struct enetc_mdio_priv priv;
124
125 priv.regs_base = bus->priv;
126 return enetc_mdio_read_priv(&priv, addr, devad, reg);
127 }
128
felix_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)129 static int felix_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
130 u16 val)
131 {
132 struct enetc_mdio_priv priv;
133
134 priv.regs_base = bus->priv;
135 return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
136 }
137
138 /* set up serdes for SGMII */
felix_init_sgmii(struct mii_dev * imdio,int pidx,bool an)139 static void felix_init_sgmii(struct mii_dev *imdio, int pidx, bool an)
140 {
141 u16 reg;
142
143 /* set up PCS lane address */
144 out_le32(FELIX_SERDES_SGMIICR1(pidx), FELIX_SERDES_SGMIICR1_SGPCS |
145 FELIX_SERDES_SGMIICR1_MDEV(pidx));
146
147 /*
148 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
149 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
150 * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
151 * but intentional.
152 */
153 reg = ENETC_PCS_IF_MODE_SGMII;
154 reg |= an ? ENETC_PCS_IF_MODE_SGMII_AN : ENETC_PCS_IF_MODE_SPEED_1G;
155 felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
156 ENETC_PCS_IF_MODE, reg);
157
158 /* Dev ability - SGMII */
159 felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
160 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
161
162 /* Adjust link timer for SGMII */
163 felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
164 ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
165 felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
166 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
167
168 reg = ENETC_PCS_CR_DEF_VAL;
169 reg |= an ? ENETC_PCS_CR_RESET_AN : ENETC_PCS_CR_RST;
170 /* restart PCS AN */
171 felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
172 ENETC_PCS_CR, reg);
173 }
174
175 /* set up MAC and serdes for (Q)SXGMII */
felix_init_sxgmii(struct mii_dev * imdio,int pidx)176 static int felix_init_sxgmii(struct mii_dev *imdio, int pidx)
177 {
178 int timeout = 1000;
179
180 /* set up transit equalization control on serdes lane */
181 out_le32(FELIX_SERDES_LNATECR0(1), FELIX_SERDES_LNATECR0_ADPT_EQ);
182
183 /*reset lane */
184 felix_mdio_write(imdio, pidx, MDIO_MMD_PCS, FELIX_PCS_CTRL,
185 FELIX_PCS_CTRL_RST);
186 while (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS,
187 FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST &&
188 --timeout) {
189 mdelay(10);
190 }
191 if (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS,
192 FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST)
193 return -ETIME;
194
195 /* Dev ability - SXGMII */
196 felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
197 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
198
199 /* Restart PCS AN */
200 felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, ENETC_PCS_CR,
201 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
202 felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
203 ENETC_PCS_REPL_LINK_TIMER_1,
204 ENETC_PCS_REPL_LINK_TIMER_1_DEF);
205 felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
206 ENETC_PCS_REPL_LINK_TIMER_2,
207 ENETC_PCS_REPL_LINK_TIMER_2_DEF);
208
209 return 0;
210 }
211
212 /* Apply protocol specific configuration to MAC, serdes as needed */
felix_start_pcs(struct udevice * dev,int port,struct phy_device * phy,struct mii_dev * imdio)213 static void felix_start_pcs(struct udevice *dev, int port,
214 struct phy_device *phy, struct mii_dev *imdio)
215 {
216 ofnode node = dsa_port_get_ofnode(dev, port);
217 bool inband_an = ofnode_eth_uses_inband_aneg(node);
218
219 switch (phy->interface) {
220 case PHY_INTERFACE_MODE_SGMII:
221 case PHY_INTERFACE_MODE_2500BASEX:
222 case PHY_INTERFACE_MODE_QSGMII:
223 felix_init_sgmii(imdio, port, inband_an);
224 break;
225 case PHY_INTERFACE_MODE_10GBASER:
226 case PHY_INTERFACE_MODE_USXGMII:
227 if (felix_init_sxgmii(imdio, port))
228 dev_err(dev, "PCS reset timeout on port %d\n", port);
229 break;
230 default:
231 break;
232 }
233 }
234
felix_init(struct udevice * dev)235 static void felix_init(struct udevice *dev)
236 {
237 struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
238 struct felix_priv *priv = dev_get_priv(dev);
239 void *base = priv->regs_base;
240 int timeout = 100;
241
242 /* Switch core reset */
243 out_le32(base + FELIX_DEVCPU_GCB_SOFT_RST, SOFT_SWC_RST);
244 while (in_le32(base + FELIX_DEVCPU_GCB_SOFT_RST) & SOFT_SWC_RST &&
245 --timeout)
246 udelay(10);
247 if (in_le32(base + FELIX_DEVCPU_GCB_SOFT_RST) & SOFT_SWC_RST)
248 dev_err(dev, "Timeout waiting for switch core reset\n");
249 timeout = 100;
250
251 /* Init core memories */
252 out_le32(base + FELIX_SYS_RAM_CTRL, FELIX_SYS_RAM_CTRL_INIT);
253 while (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT &&
254 --timeout)
255 udelay(10);
256 if (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT)
257 dev_err(dev, "Timeout waiting for switch memories\n");
258
259 /* Start switch core, set up ES0, IS1, IS2 */
260 out_le32(base + FELIX_SYS_SYSTEM, FELIX_SYS_SYSTEM_EN);
261 out_le32(base + FELIX_ES0_TCAM_CTRL, FELIX_ES0_TCAM_CTRL_EN);
262 out_le32(base + FELIX_IS1_TCAM_CTRL, FELIX_IS1_TCAM_CTRL_EN);
263 out_le32(base + FELIX_IS2_TCAM_CTRL, FELIX_IS2_TCAM_CTRL_EN);
264 udelay(20);
265
266 priv->imdio.read = felix_mdio_read;
267 priv->imdio.write = felix_mdio_write;
268 priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
269 strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
270
271 /* set up CPU port */
272 out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG,
273 FELIX_QSYS_SYSTEM_EXT_CPU_PORT(pdata->cpu_port));
274 out_le32(base + FELIX_SYS_SYSTEM_PORT_MODE(pdata->cpu_port),
275 FELIX_SYS_SYSTEM_PORT_MODE_CPU);
276 }
277
278 /*
279 * Probe Felix:
280 * - enable the PCI function
281 * - map BAR 4
282 * - init switch core and port registers
283 */
felix_probe(struct udevice * dev)284 static int felix_probe(struct udevice *dev)
285 {
286 struct felix_priv *priv = dev_get_priv(dev);
287 int err;
288
289 if (ofnode_valid(dev_ofnode(dev)) &&
290 !ofnode_is_enabled(dev_ofnode(dev))) {
291 dev_dbg(dev, "switch disabled\n");
292 return -ENODEV;
293 }
294
295 priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
296 if (!priv->imdio_base) {
297 dev_err(dev, "failed to map BAR0\n");
298 return -EINVAL;
299 }
300
301 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, 0);
302 if (!priv->regs_base) {
303 dev_err(dev, "failed to map BAR4\n");
304 return -EINVAL;
305 }
306
307 /* register internal MDIO for debug */
308 if (!miiphy_get_dev_by_name(dev->name)) {
309 struct mii_dev *mii_bus;
310
311 mii_bus = mdio_alloc();
312 if (!mii_bus)
313 return -ENOMEM;
314
315 mii_bus->read = felix_mdio_read;
316 mii_bus->write = felix_mdio_write;
317 mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
318 strlcpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
319 err = mdio_register(mii_bus);
320 if (err) {
321 mdio_free(mii_bus);
322 return err;
323 }
324 }
325
326 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
327
328 dsa_set_tagging(dev, FELIX_DSA_TAG_LEN, 0);
329
330 /* set up registers */
331 felix_init(dev);
332
333 return 0;
334 }
335
felix_port_probe(struct udevice * dev,int port,struct phy_device * phy)336 static int felix_port_probe(struct udevice *dev, int port,
337 struct phy_device *phy)
338 {
339 int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
340 struct felix_priv *priv = dev_get_priv(dev);
341
342 phy->supported &= supported;
343 phy->advertising &= supported;
344
345 felix_start_pcs(dev, port, phy, &priv->imdio);
346
347 return phy_config(phy);
348 }
349
felix_port_enable(struct udevice * dev,int port,struct phy_device * phy)350 static int felix_port_enable(struct udevice *dev, int port,
351 struct phy_device *phy)
352 {
353 struct felix_priv *priv = dev_get_priv(dev);
354 void *base = priv->regs_base;
355
356 /* Set up MAC registers */
357 out_le32(base + FELIX_GMII_CLOCK_CFG(port),
358 FELIX_GMII_CLOCK_CFG_LINK_1G);
359
360 out_le32(base + FELIX_GMII_MAC_IFG_CFG(port),
361 FELIX_GMII_MAC_IFG_CFG_DEF);
362
363 out_le32(base + FELIX_GMII_MAC_ENA_CFG(port),
364 FELIX_GMII_MAX_ENA_CFG_TX | FELIX_GMII_MAX_ENA_CFG_RX);
365
366 out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(port),
367 FELIX_QSYS_SYSTEM_SW_PORT_ENA |
368 FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
369 FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
370
371 return phy_startup(phy);
372 }
373
felix_port_disable(struct udevice * dev,int pidx,struct phy_device * phy)374 static void felix_port_disable(struct udevice *dev, int pidx,
375 struct phy_device *phy)
376 {
377 struct felix_priv *priv = dev_get_priv(dev);
378 void *base = priv->regs_base;
379
380 out_le32(base + FELIX_GMII_MAC_ENA_CFG(pidx), 0);
381
382 out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(pidx),
383 FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
384 FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
385
386 /*
387 * we don't call phy_shutdown here to avoid waiting next time we use
388 * the port, but the downside is that remote side will think we're
389 * actively processing traffic although we are not.
390 */
391 }
392
felix_xmit(struct udevice * dev,int pidx,void * packet,int length)393 static int felix_xmit(struct udevice *dev, int pidx, void *packet, int length)
394 {
395 struct felix_dsa_tag *tag = packet;
396
397 tag->magic = FELIX_DSA_TAG_MAGIC;
398 tag->meta[FELIX_DSA_TAG_INJ_PORT] = FELIX_DSA_TAG_INJ_PORT_SET(pidx);
399
400 return 0;
401 }
402
felix_rcv(struct udevice * dev,int * pidx,void * packet,int length)403 static int felix_rcv(struct udevice *dev, int *pidx, void *packet, int length)
404 {
405 struct felix_dsa_tag *tag = packet;
406
407 if (tag->magic != FELIX_DSA_TAG_MAGIC)
408 return -EINVAL;
409
410 *pidx = FELIX_DSA_TAG_EXT_PORT_GET(tag->meta[FELIX_DSA_TAG_EXT_PORT]);
411
412 return 0;
413 }
414
415 static const struct dsa_ops felix_dsa_ops = {
416 .port_probe = felix_port_probe,
417 .port_enable = felix_port_enable,
418 .port_disable = felix_port_disable,
419 .xmit = felix_xmit,
420 .rcv = felix_rcv,
421 };
422
423 U_BOOT_DRIVER(felix_ethsw) = {
424 .name = "felix-switch",
425 .id = UCLASS_DSA,
426 .probe = felix_probe,
427 .ops = &felix_dsa_ops,
428 .priv_auto = sizeof(struct felix_priv),
429 };
430
431 static struct pci_device_id felix_ethsw_ids[] = {
432 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_FELIX_ETHSW) },
433 {}
434 };
435
436 U_BOOT_PCI_DEVICE(felix_ethsw, felix_ethsw_ids);
437