1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 *
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
7 */
8
9 #include <cpu_func.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <asm/cache.h>
17 #include <asm/io.h>
18 #include <pci.h>
19 #include <linux/delay.h>
20
21 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
22
23 #define PCNET_DEBUG1(fmt,args...) \
24 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
25 #define PCNET_DEBUG2(fmt,args...) \
26 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
27
28 /*
29 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
32 */
33 #define PCNET_LOG_TX_BUFFERS 0
34 #define PCNET_LOG_RX_BUFFERS 2
35
36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
38
39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
41
42 #define PKT_BUF_SZ 1544
43
44 /* The PCNET Rx and Tx ring descriptors. */
45 struct pcnet_rx_head {
46 u32 base;
47 s16 buf_length;
48 s16 status;
49 u32 msg_length;
50 u32 reserved;
51 };
52
53 struct pcnet_tx_head {
54 u32 base;
55 s16 length;
56 s16 status;
57 u32 misc;
58 u32 reserved;
59 };
60
61 /* The PCNET 32-Bit initialization block, described in databook. */
62 struct pcnet_init_block {
63 u16 mode;
64 u16 tlen_rlen;
65 u8 phys_addr[6];
66 u16 reserved;
67 u32 filter[2];
68 /* Receive and transmit ring base, along with extra bits. */
69 u32 rx_ring;
70 u32 tx_ring;
71 u32 reserved2;
72 };
73
74 struct pcnet_uncached_priv {
75 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
76 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
77 struct pcnet_init_block init_block;
78 } __aligned(ARCH_DMA_MINALIGN);
79
80 struct pcnet_priv {
81 struct pcnet_uncached_priv ucp;
82 /* Receive Buffer space */
83 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
84 struct pcnet_uncached_priv *uc;
85 struct udevice *dev;
86 const char *name;
87 void __iomem *iobase;
88 u8 *enetaddr;
89 u16 status;
90 int cur_rx;
91 int cur_tx;
92 };
93
94 /* Offsets from base I/O address for WIO mode */
95 #define PCNET_RDP 0x10
96 #define PCNET_RAP 0x12
97 #define PCNET_RESET 0x14
98 #define PCNET_BDP 0x16
99
pcnet_read_csr(struct pcnet_priv * lp,int index)100 static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
101 {
102 writew(index, lp->iobase + PCNET_RAP);
103 return readw(lp->iobase + PCNET_RDP);
104 }
105
pcnet_write_csr(struct pcnet_priv * lp,int index,u16 val)106 static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
107 {
108 writew(index, lp->iobase + PCNET_RAP);
109 writew(val, lp->iobase + PCNET_RDP);
110 }
111
pcnet_read_bcr(struct pcnet_priv * lp,int index)112 static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
113 {
114 writew(index, lp->iobase + PCNET_RAP);
115 return readw(lp->iobase + PCNET_BDP);
116 }
117
pcnet_write_bcr(struct pcnet_priv * lp,int index,u16 val)118 static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
119 {
120 writew(index, lp->iobase + PCNET_RAP);
121 writew(val, lp->iobase + PCNET_BDP);
122 }
123
pcnet_reset(struct pcnet_priv * lp)124 static void pcnet_reset(struct pcnet_priv *lp)
125 {
126 readw(lp->iobase + PCNET_RESET);
127 }
128
pcnet_check(struct pcnet_priv * lp)129 static int pcnet_check(struct pcnet_priv *lp)
130 {
131 writew(88, lp->iobase + PCNET_RAP);
132 return readw(lp->iobase + PCNET_RAP) == 88;
133 }
134
pcnet_virt_to_mem(struct pcnet_priv * lp,void * addr)135 static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
136 {
137 void *virt_addr = addr;
138
139 return dm_pci_virt_to_mem(lp->dev, virt_addr);
140 }
141
142 static struct pci_device_id supported[] = {
143 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
144 {}
145 };
146
pcnet_probe_common(struct pcnet_priv * lp)147 static int pcnet_probe_common(struct pcnet_priv *lp)
148 {
149 int chip_version;
150 char *chipname;
151 int i;
152
153 /* Reset the PCnet controller */
154 pcnet_reset(lp);
155
156 /* Check if register access is working */
157 if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
158 printf("%s: CSR register access check failed\n", lp->name);
159 return -1;
160 }
161
162 /* Identify the chip */
163 chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
164 if ((chip_version & 0xfff) != 0x003)
165 return -1;
166 chip_version = (chip_version >> 12) & 0xffff;
167 switch (chip_version) {
168 case 0x2621:
169 chipname = "PCnet/PCI II 79C970A"; /* PCI */
170 break;
171 case 0x2625:
172 chipname = "PCnet/FAST III 79C973"; /* PCI */
173 break;
174 case 0x2627:
175 chipname = "PCnet/FAST III 79C975"; /* PCI */
176 break;
177 default:
178 printf("%s: PCnet version %#x not supported\n",
179 lp->name, chip_version);
180 return -1;
181 }
182
183 PCNET_DEBUG1("AMD %s\n", chipname);
184
185 /*
186 * In most chips, after a chip reset, the ethernet address is read from
187 * the station address PROM at the base address and programmed into the
188 * "Physical Address Registers" CSR12-14.
189 */
190 for (i = 0; i < 3; i++) {
191 unsigned int val;
192
193 val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
194 /* There may be endianness issues here. */
195 lp->enetaddr[2 * i] = val & 0x0ff;
196 lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
197 }
198
199 return 0;
200 }
201
pcnet_init_common(struct pcnet_priv * lp)202 static int pcnet_init_common(struct pcnet_priv *lp)
203 {
204 struct pcnet_uncached_priv *uc;
205 int i, val;
206 unsigned long addr;
207
208 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
209
210 /* Switch pcnet to 32bit mode */
211 pcnet_write_bcr(lp, 20, 2);
212
213 /* Set/reset autoselect bit */
214 val = pcnet_read_bcr(lp, 2) & ~2;
215 val |= 2;
216 pcnet_write_bcr(lp, 2, val);
217
218 /* Enable auto negotiate, setup, disable fd */
219 val = pcnet_read_bcr(lp, 32) & ~0x98;
220 val |= 0x20;
221 pcnet_write_bcr(lp, 32, val);
222
223 /*
224 * Enable NOUFLO on supported controllers, with the transmit
225 * start point set to the full packet. This will cause entire
226 * packets to be buffered by the ethernet controller before
227 * transmission, eliminating underflows which are common on
228 * slower devices. Controllers which do not support NOUFLO will
229 * simply be left with a larger transmit FIFO threshold.
230 */
231 val = pcnet_read_bcr(lp, 18);
232 val |= 1 << 11;
233 pcnet_write_bcr(lp, 18, val);
234 val = pcnet_read_csr(lp, 80);
235 val |= 0x3 << 10;
236 pcnet_write_csr(lp, 80, val);
237
238 uc = lp->uc;
239
240 uc->init_block.mode = cpu_to_le16(0x0000);
241 uc->init_block.filter[0] = 0x00000000;
242 uc->init_block.filter[1] = 0x00000000;
243
244 /*
245 * Initialize the Rx ring.
246 */
247 lp->cur_rx = 0;
248 for (i = 0; i < RX_RING_SIZE; i++) {
249 addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
250 uc->rx_ring[i].base = cpu_to_le32(addr);
251 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
252 uc->rx_ring[i].status = cpu_to_le16(0x8000);
253 PCNET_DEBUG1
254 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
255 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
256 uc->rx_ring[i].status);
257 }
258
259 /*
260 * Initialize the Tx ring. The Tx buffer address is filled in as
261 * needed, but we do need to clear the upper ownership bit.
262 */
263 lp->cur_tx = 0;
264 for (i = 0; i < TX_RING_SIZE; i++) {
265 uc->tx_ring[i].base = 0;
266 uc->tx_ring[i].status = 0;
267 }
268
269 /*
270 * Setup Init Block.
271 */
272 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
273
274 for (i = 0; i < 6; i++) {
275 lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
276 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
277 }
278
279 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
280 RX_RING_LEN_BITS);
281 addr = pcnet_virt_to_mem(lp, uc->rx_ring);
282 uc->init_block.rx_ring = cpu_to_le32(addr);
283 addr = pcnet_virt_to_mem(lp, uc->tx_ring);
284 uc->init_block.tx_ring = cpu_to_le32(addr);
285
286 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
287 uc->init_block.tlen_rlen,
288 uc->init_block.rx_ring, uc->init_block.tx_ring);
289
290 /*
291 * Tell the controller where the Init Block is located.
292 */
293 barrier();
294 addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
295 pcnet_write_csr(lp, 1, addr & 0xffff);
296 pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
297
298 pcnet_write_csr(lp, 4, 0x0915);
299 pcnet_write_csr(lp, 0, 0x0001); /* start */
300
301 /* Wait for Init Done bit */
302 for (i = 10000; i > 0; i--) {
303 if (pcnet_read_csr(lp, 0) & 0x0100)
304 break;
305 udelay(10);
306 }
307 if (i <= 0) {
308 printf("%s: TIMEOUT: controller init failed\n", lp->name);
309 pcnet_reset(lp);
310 return -1;
311 }
312
313 /*
314 * Finally start network controller operation.
315 */
316 pcnet_write_csr(lp, 0, 0x0002);
317
318 return 0;
319 }
320
pcnet_send_common(struct pcnet_priv * lp,void * packet,int pkt_len)321 static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
322 {
323 int i, status;
324 u32 addr;
325 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
326
327 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
328 packet);
329
330 flush_dcache_range((unsigned long)packet,
331 (unsigned long)packet + pkt_len);
332
333 /* Wait for completion by testing the OWN bit */
334 for (i = 1000; i > 0; i--) {
335 status = readw(&entry->status);
336 if ((status & 0x8000) == 0)
337 break;
338 udelay(100);
339 PCNET_DEBUG2(".");
340 }
341 if (i <= 0) {
342 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
343 lp->name, lp->cur_tx, status);
344 pkt_len = 0;
345 goto failure;
346 }
347
348 /*
349 * Setup Tx ring. Caution: the write order is important here,
350 * set the status with the "ownership" bits last.
351 */
352 addr = pcnet_virt_to_mem(lp, packet);
353 writew(-pkt_len, &entry->length);
354 writel(0, &entry->misc);
355 writel(addr, &entry->base);
356 writew(0x8300, &entry->status);
357
358 /* Trigger an immediate send poll. */
359 pcnet_write_csr(lp, 0, 0x0008);
360
361 failure:
362 if (++lp->cur_tx >= TX_RING_SIZE)
363 lp->cur_tx = 0;
364
365 PCNET_DEBUG2("done\n");
366 return pkt_len;
367 }
368
pcnet_recv_common(struct pcnet_priv * lp,unsigned char ** bufp)369 static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
370 {
371 struct pcnet_rx_head *entry;
372 unsigned char *buf;
373 int pkt_len = 0;
374 u16 err_status;
375
376 entry = &lp->uc->rx_ring[lp->cur_rx];
377 /*
378 * If we own the next entry, it's a new packet. Send it up.
379 */
380 lp->status = readw(&entry->status);
381 if ((lp->status & 0x8000) != 0)
382 return 0;
383 err_status = lp->status >> 8;
384
385 if (err_status != 0x03) { /* There was an error. */
386 printf("%s: Rx%d", lp->name, lp->cur_rx);
387 PCNET_DEBUG1(" (status=0x%x)", err_status);
388 if (err_status & 0x20)
389 printf(" Frame");
390 if (err_status & 0x10)
391 printf(" Overflow");
392 if (err_status & 0x08)
393 printf(" CRC");
394 if (err_status & 0x04)
395 printf(" Fifo");
396 printf(" Error\n");
397 lp->status &= 0x03ff;
398 return 0;
399 }
400
401 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
402 if (pkt_len < 60) {
403 printf("%s: Rx%d: invalid packet length %d\n",
404 lp->name, lp->cur_rx, pkt_len);
405 return 0;
406 }
407
408 *bufp = lp->rx_buf[lp->cur_rx];
409 invalidate_dcache_range((unsigned long)*bufp,
410 (unsigned long)*bufp + pkt_len);
411
412 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
413 lp->cur_rx, pkt_len, buf);
414
415 return pkt_len;
416 }
417
pcnet_free_pkt_common(struct pcnet_priv * lp,unsigned int len)418 static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
419 {
420 struct pcnet_rx_head *entry;
421
422 entry = &lp->uc->rx_ring[lp->cur_rx];
423
424 lp->status |= 0x8000;
425 writew(lp->status, &entry->status);
426
427 if (++lp->cur_rx >= RX_RING_SIZE)
428 lp->cur_rx = 0;
429 }
430
pcnet_halt_common(struct pcnet_priv * lp)431 static void pcnet_halt_common(struct pcnet_priv *lp)
432 {
433 int i;
434
435 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
436
437 /* Reset the PCnet controller */
438 pcnet_reset(lp);
439
440 /* Wait for Stop bit */
441 for (i = 1000; i > 0; i--) {
442 if (pcnet_read_csr(lp, 0) & 0x4)
443 break;
444 udelay(10);
445 }
446 if (i <= 0)
447 printf("%s: TIMEOUT: controller reset failed\n", lp->name);
448 }
449
pcnet_start(struct udevice * dev)450 static int pcnet_start(struct udevice *dev)
451 {
452 struct eth_pdata *plat = dev_get_plat(dev);
453 struct pcnet_priv *priv = dev_get_priv(dev);
454
455 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
456
457 return pcnet_init_common(priv);
458 }
459
pcnet_stop(struct udevice * dev)460 static void pcnet_stop(struct udevice *dev)
461 {
462 struct pcnet_priv *priv = dev_get_priv(dev);
463
464 pcnet_halt_common(priv);
465 }
466
pcnet_send(struct udevice * dev,void * packet,int length)467 static int pcnet_send(struct udevice *dev, void *packet, int length)
468 {
469 struct pcnet_priv *priv = dev_get_priv(dev);
470 int ret;
471
472 ret = pcnet_send_common(priv, packet, length);
473
474 return ret ? 0 : -ETIMEDOUT;
475 }
476
pcnet_recv(struct udevice * dev,int flags,uchar ** packetp)477 static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
478 {
479 struct pcnet_priv *priv = dev_get_priv(dev);
480
481 return pcnet_recv_common(priv, packetp);
482 }
483
pcnet_free_pkt(struct udevice * dev,uchar * packet,int length)484 static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
485 {
486 struct pcnet_priv *priv = dev_get_priv(dev);
487
488 pcnet_free_pkt_common(priv, length);
489
490 return 0;
491 }
492
pcnet_bind(struct udevice * dev)493 static int pcnet_bind(struct udevice *dev)
494 {
495 static int card_number;
496 char name[16];
497
498 sprintf(name, "pcnet#%u", card_number++);
499
500 return device_set_name(dev, name);
501 }
502
pcnet_probe(struct udevice * dev)503 static int pcnet_probe(struct udevice *dev)
504 {
505 struct eth_pdata *plat = dev_get_plat(dev);
506 struct pcnet_priv *lp = dev_get_priv(dev);
507 u16 command, status;
508 u32 iobase;
509 int ret;
510
511 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
512 iobase &= ~0xf;
513
514 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
515 sizeof(lp->ucp), MAP_NOCACHE);
516 lp->dev = dev;
517 lp->name = dev->name;
518 lp->enetaddr = plat->enetaddr;
519 lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
520
521 flush_dcache_range((unsigned long)lp,
522 (unsigned long)lp + sizeof(*lp));
523
524 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
525 dm_pci_write_config16(dev, PCI_COMMAND, command);
526 dm_pci_read_config16(dev, PCI_COMMAND, &status);
527 if ((status & command) != command) {
528 printf("%s: Couldn't enable IO access or Bus Mastering\n",
529 lp->name);
530 return -EINVAL;
531 }
532
533 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
534
535 ret = pcnet_probe_common(lp);
536 if (ret)
537 return ret;
538
539 return 0;
540 }
541
542 static const struct eth_ops pcnet_ops = {
543 .start = pcnet_start,
544 .send = pcnet_send,
545 .recv = pcnet_recv,
546 .stop = pcnet_stop,
547 .free_pkt = pcnet_free_pkt,
548 };
549
550 U_BOOT_DRIVER(eth_pcnet) = {
551 .name = "eth_pcnet",
552 .id = UCLASS_ETH,
553 .bind = pcnet_bind,
554 .probe = pcnet_probe,
555 .ops = &pcnet_ops,
556 .priv_auto = sizeof(struct pcnet_priv),
557 .plat_auto = sizeof(struct eth_pdata),
558 .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
559 };
560
561 U_BOOT_PCI_DEVICE(eth_pcnet, supported);
562