1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Cortina CS4315/CS4340 10G PHY drivers
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 */
9
10 #include <config.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <linux/ctype.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/err.h>
17 #include <phy.h>
18
19 #define PHY_ID_RTL8211_EXT 0x001cc910
20 #define PHY_ID_RTL8211_INT 0x001cc980
21 #define PHY_ID_MASK 0xFFFFFFF0
22
__internal_phy_init(struct phy_device * phydev,int reset_phy)23 static void __internal_phy_init(struct phy_device *phydev, int reset_phy)
24 {
25 u8 phy_addr;
26 u16 data;
27
28 /* should initialize 4 GPHYs at once */
29 for (phy_addr = 4; phy_addr > 0; phy_addr--) {
30 phydev->addr = phy_addr;
31 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0BC6);
32 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x0053);
33 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x4003);
34 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x7e01);
35 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A42);
36 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A40);
37 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1140);
38 }
39
40 /* workaround to fix GPHY fail */
41 for (phy_addr = 1; phy_addr < 5; phy_addr++) {
42 /* Clear clock fail interrupt */
43 phydev->addr = phy_addr;
44 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
45 data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
46 if (data == 0x10) {
47 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
48 data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
49 printf("%s: read again.\n", __func__);
50 }
51
52 printf("%s: phy_addr=%d, read register 19, value=0x%x\n",
53 __func__, phy_addr, data);
54 }
55 }
56
__external_phy_init(struct phy_device * phydev,int reset_phy)57 static void __external_phy_init(struct phy_device *phydev, int reset_phy)
58 {
59 u16 val;
60
61 /* Disable response PHYAD=0 function of RTL8211 series PHY */
62 /* REG31 write 0x0007, set to extension page */
63 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0007);
64
65 /* REG30 write 0x002C, set to extension page 44 */
66 phy_write(phydev, MDIO_DEVAD_NONE, 30, 0x002C);
67
68 /*
69 * REG27 write bit[2] = 0 disable response PHYAD = 0 function.
70 * we should read REG27 and clear bit[2], and write back
71 */
72 val = phy_read(phydev, MDIO_DEVAD_NONE, 27);
73 val &= ~(1 << 2);
74 phy_write(phydev, MDIO_DEVAD_NONE, 27, val);
75
76 /* REG31 write 0x0000, back to page0 */
77 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
78 }
79
rtl8211_external_config(struct phy_device * phydev)80 static int rtl8211_external_config(struct phy_device *phydev)
81 {
82 __external_phy_init(phydev, 0);
83 printf("%s: initialize RTL8211 external done.\n", __func__);
84 return 0;
85 }
86
rtl8211_internal_config(struct phy_device * phydev)87 static int rtl8211_internal_config(struct phy_device *phydev)
88 {
89 struct phy_device phydev_init;
90
91 memcpy(&phydev_init, phydev, sizeof(struct phy_device));
92 /* should initialize 4 GPHYs at once */
93 __internal_phy_init(&phydev_init, 0);
94 printf("%s: initialize RTL8211 internal done.\n", __func__);
95 return 0;
96 }
97
rtl8211_probe(struct phy_device * phydev)98 static int rtl8211_probe(struct phy_device *phydev)
99 {
100 /* disable reset behavior */
101 phydev->flags = PHY_FLAG_BROKEN_RESET;
102 return 0;
103 }
104
105 /* Support for RTL8211 External PHY */
106 U_BOOT_PHY_DRIVER(rtl8211_external) = {
107 .name = "Cortina RTL8211 External",
108 .uid = PHY_ID_RTL8211_EXT,
109 .mask = PHY_ID_MASK,
110 .features = PHY_GBIT_FEATURES,
111 .config = &rtl8211_external_config,
112 .probe = &rtl8211_probe,
113 .startup = &genphy_startup,
114 };
115
116 /* Support for RTL8211 Internal PHY */
117 U_BOOT_PHY_DRIVER(rtl8211_internal) = {
118 .name = "Cortina RTL8211 Inrernal",
119 .uid = PHY_ID_RTL8211_INT,
120 .mask = PHY_ID_MASK,
121 .features = PHY_GBIT_FEATURES,
122 .config = &rtl8211_internal_config,
123 .probe = &rtl8211_probe,
124 .startup = &genphy_startup,
125 };
126