1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI PHY drivers
4 *
5 */
6 #include <log.h>
7 #include <phy.h>
8 #include <dm/devres.h>
9 #include <linux/bitops.h>
10 #include <linux/compat.h>
11 #include <malloc.h>
12 #include <linux/printk.h>
13
14 #include <dm.h>
15 #include <dt-bindings/net/ti-dp83867.h>
16
17 #include "ti_phy_init.h"
18
19 /* TI DP83867 */
20 #define DP83867_DEVADDR 0x1f
21
22 #define MII_DP83867_PHYCTRL 0x10
23 #define MII_DP83867_MICR 0x12
24 #define MII_DP83867_CFG2 0x14
25 #define MII_DP83867_BISCR 0x16
26 #define DP83867_CTRL 0x1f
27
28 /* Extended Registers */
29 #define DP83867_CFG4 0x0031
30 #define DP83867_RGMIICTL 0x0032
31 #define DP83867_STRAP_STS1 0x006E
32 #define DP83867_STRAP_STS2 0x006f
33 #define DP83867_RGMIIDCTL 0x0086
34 #define DP83867_IO_MUX_CFG 0x0170
35 #define DP83867_SGMIICTL 0x00D3
36
37 #define DP83867_SW_RESET BIT(15)
38 #define DP83867_SW_RESTART BIT(14)
39
40 /* MICR Interrupt bits */
41 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
42 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
43 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
44 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
45 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
46 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
47 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
48 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
49 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
50 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
51 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
52 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
53
54 /* RGMIICTL bits */
55 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
56 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
57
58 /* STRAP_STS1 bits */
59 #define DP83867_STRAP_STS1_RESERVED BIT(11)
60
61 /* STRAP_STS2 bits */
62 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
63 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
64 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
65 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
66 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
67
68 /* PHY CTRL bits */
69 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
70 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
71 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
72 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
73 #define DP83867_MDI_CROSSOVER 5
74 #define DP83867_MDI_CROSSOVER_MDIX 2
75 #define DP83867_PHYCTRL_SGMIIEN 0x0800
76 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
77 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
78
79 /* RGMIIDCTL bits */
80 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
81 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
82 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
83
84 /* CFG2 bits */
85 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
86 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
87 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
88 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
89 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
90 #define MII_DP83867_CFG2_MASK 0x003F
91
92 /* User setting - can be taken from DTS */
93 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
94
95 /* IO_MUX_CFG bits */
96 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
97
98 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
99 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
100 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
101 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
102 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
103 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
104
105 /* CFG4 bits */
106 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
107
108 /* SGMIICTL bits */
109 #define DP83867_SGMII_TYPE BIT(14)
110
111 enum {
112 DP83867_PORT_MIRRORING_KEEP,
113 DP83867_PORT_MIRRORING_EN,
114 DP83867_PORT_MIRRORING_DIS,
115 };
116
117 struct dp83867_private {
118 u32 rx_id_delay;
119 u32 tx_id_delay;
120 int fifo_depth;
121 int io_impedance;
122 bool rxctrl_strap_quirk;
123 int port_mirroring;
124 bool set_clk_output;
125 unsigned int clk_output_sel;
126 bool sgmii_ref_clk_en;
127 };
128
dp83867_config_port_mirroring(struct phy_device * phydev)129 static int dp83867_config_port_mirroring(struct phy_device *phydev)
130 {
131 struct dp83867_private *dp83867 =
132 (struct dp83867_private *)phydev->priv;
133 u16 val;
134
135 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
136
137 if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
138 val |= DP83867_CFG4_PORT_MIRROR_EN;
139 else
140 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
141
142 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
143
144 return 0;
145 }
146
147 /**
148 * dp83867_data_init - Convenience function for setting PHY specific data
149 *
150 * @phydev: the phy_device struct
151 */
dp83867_of_init(struct phy_device * phydev)152 static int dp83867_of_init(struct phy_device *phydev)
153 {
154 struct dp83867_private *dp83867 = phydev->priv;
155 ofnode node;
156 int ret;
157
158 node = phy_get_ofnode(phydev);
159 if (!ofnode_valid(node))
160 return 0;
161
162 /* Optional configuration */
163 ret = ofnode_read_u32(node, "ti,clk-output-sel",
164 &dp83867->clk_output_sel);
165 /* If not set, keep default */
166 if (!ret) {
167 dp83867->set_clk_output = true;
168 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
169 * DP83867_CLK_O_SEL_OFF.
170 */
171 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
172 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
173 pr_debug("ti,clk-output-sel value %u out of range\n",
174 dp83867->clk_output_sel);
175 return -EINVAL;
176 }
177 }
178
179 if (ofnode_read_bool(node, "ti,max-output-impedance"))
180 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
181 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
182 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
183 else
184 dp83867->io_impedance = -EINVAL;
185
186 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
187 dp83867->rxctrl_strap_quirk = true;
188
189 /* Existing behavior was to use default pin strapping delay in rgmii
190 * mode, but rgmii should have meant no delay. Warn existing users.
191 */
192 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
193 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
194 DP83867_STRAP_STS2);
195 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
196 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
197 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
198 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
199
200 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
201 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
202 pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
203 "Should be 'rgmii-id' to use internal delays\n");
204 }
205
206 /* RX delay *must* be specified if internal delay of RX is used. */
207 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
208 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
209 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
210 &dp83867->rx_id_delay);
211 if (ret) {
212 pr_debug("ti,rx-internal-delay must be specified\n");
213 return ret;
214 }
215 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
216 pr_debug("ti,rx-internal-delay value of %u out of range\n",
217 dp83867->rx_id_delay);
218 return -EINVAL;
219 }
220 }
221
222 /* TX delay *must* be specified if internal delay of RX is used. */
223 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
224 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
225 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
226 &dp83867->tx_id_delay);
227 if (ret) {
228 debug("ti,tx-internal-delay must be specified\n");
229 return ret;
230 }
231 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
232 pr_debug("ti,tx-internal-delay value of %u out of range\n",
233 dp83867->tx_id_delay);
234 return -EINVAL;
235 }
236 }
237
238 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
239 DEFAULT_FIFO_DEPTH);
240 if (ofnode_read_bool(node, "enet-phy-lane-swap"))
241 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
242
243 if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
244 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
245
246 if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
247 dp83867->sgmii_ref_clk_en = true;
248
249 return 0;
250 }
251
dp83867_config(struct phy_device * phydev)252 static int dp83867_config(struct phy_device *phydev)
253 {
254 struct dp83867_private *dp83867;
255 int val, delay, cfg2;
256 int ret, bs;
257
258 dp83867 = (struct dp83867_private *)phydev->priv;
259
260 ret = dp83867_of_init(phydev);
261 if (ret)
262 return ret;
263
264 /* Restart the PHY. */
265 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
266 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
267 val | DP83867_SW_RESTART);
268
269 /* Mode 1 or 2 workaround */
270 if (dp83867->rxctrl_strap_quirk) {
271 val = phy_read_mmd(phydev, DP83867_DEVADDR,
272 DP83867_CFG4);
273 val &= ~BIT(7);
274 phy_write_mmd(phydev, DP83867_DEVADDR,
275 DP83867_CFG4, val);
276 }
277
278 if (phy_interface_is_rgmii(phydev)) {
279 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
280 if (val < 0) {
281 ret = val;
282 goto err_out;
283 }
284
285 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
286 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
287
288 /* Do not force link good */
289 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
290
291 /* The code below checks if "port mirroring" N/A MODE4 has been
292 * enabled during power on bootstrap.
293 *
294 * Such N/A mode enabled by mistake can put PHY IC in some
295 * internal testing mode and disable RGMII transmission.
296 *
297 * In this particular case one needs to check STRAP_STS1
298 * register's bit 11 (marked as RESERVED).
299 */
300
301 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
302 if (bs & DP83867_STRAP_STS1_RESERVED)
303 val &= ~DP83867_PHYCR_RESERVED_MASK;
304
305 ret = phy_write(phydev, MDIO_DEVAD_NONE,
306 MII_DP83867_PHYCTRL, val);
307
308 val = phy_read_mmd(phydev, DP83867_DEVADDR,
309 DP83867_RGMIICTL);
310
311 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
312 DP83867_RGMII_RX_CLK_DELAY_EN);
313 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
314 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
315 DP83867_RGMII_RX_CLK_DELAY_EN);
316
317 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
318 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
319
320 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
321 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
322
323 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
324
325 delay = (dp83867->rx_id_delay |
326 (dp83867->tx_id_delay <<
327 DP83867_RGMII_TX_CLK_DELAY_SHIFT));
328
329 phy_write_mmd(phydev, DP83867_DEVADDR,
330 DP83867_RGMIIDCTL, delay);
331 }
332
333 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
334 if (dp83867->sgmii_ref_clk_en)
335 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
336 DP83867_SGMII_TYPE);
337
338 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
339 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
340
341 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
342 cfg2 &= MII_DP83867_CFG2_MASK;
343 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
344 MII_DP83867_CFG2_SGMII_AUTONEGEN |
345 MII_DP83867_CFG2_SPEEDOPT_ENH |
346 MII_DP83867_CFG2_SPEEDOPT_CNT |
347 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
348 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
349
350 phy_write_mmd(phydev, DP83867_DEVADDR,
351 DP83867_RGMIICTL, 0x0);
352
353 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
354 DP83867_PHYCTRL_SGMIIEN |
355 (DP83867_MDI_CROSSOVER_MDIX <<
356 DP83867_MDI_CROSSOVER) |
357 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
358 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
360 }
361
362 if (dp83867->io_impedance >= 0) {
363 val = phy_read_mmd(phydev,
364 DP83867_DEVADDR,
365 DP83867_IO_MUX_CFG);
366 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
367 val |= dp83867->io_impedance &
368 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
369 phy_write_mmd(phydev, DP83867_DEVADDR,
370 DP83867_IO_MUX_CFG, val);
371 }
372
373 if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
374 dp83867_config_port_mirroring(phydev);
375
376 /* Clock output selection if muxing property is set */
377 if (dp83867->set_clk_output) {
378 val = phy_read_mmd(phydev, DP83867_DEVADDR,
379 DP83867_IO_MUX_CFG);
380
381 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
382 val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
383 } else {
384 val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
385 DP83867_IO_MUX_CFG_CLK_O_DISABLE);
386 val |= dp83867->clk_output_sel <<
387 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
388 }
389 phy_write_mmd(phydev, DP83867_DEVADDR,
390 DP83867_IO_MUX_CFG, val);
391 }
392
393 genphy_config_aneg(phydev);
394 return 0;
395
396 err_out:
397 return ret;
398 }
399
dp83867_probe(struct phy_device * phydev)400 static int dp83867_probe(struct phy_device *phydev)
401 {
402 struct dp83867_private *dp83867;
403
404 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
405 if (!dp83867)
406 return -ENOMEM;
407
408 phydev->priv = dp83867;
409 return 0;
410 }
411
412 U_BOOT_PHY_DRIVER(dp83867) = {
413 .name = "TI DP83867",
414 .uid = 0x2000a231,
415 .mask = 0xfffffff0,
416 .features = PHY_GBIT_FEATURES,
417 .probe = dp83867_probe,
418 .config = &dp83867_config,
419 .startup = &genphy_startup,
420 .shutdown = &genphy_shutdown,
421 };
422