1 // SPDX-License-Identifier: GPL-2.0+
2 #include <phy.h>
3 #include <linux/bitfield.h>
4
5 #define XWAY_MDIO_MIICTRL 0x17 /* mii control */
6
7 #define XWAY_MDIO_MIICTRL_RXSKEW_MASK GENMASK(14, 12)
8 #define XWAY_MDIO_MIICTRL_TXSKEW_MASK GENMASK(10, 8)
9
xway_config(struct phy_device * phydev)10 static int xway_config(struct phy_device *phydev)
11 {
12 ofnode node = phy_get_ofnode(phydev);
13 u32 val = 0;
14
15 if (ofnode_valid(node)) {
16 u32 rx_delay, tx_delay;
17
18 rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
19 tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
20 val |= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, rx_delay / 500);
21 val |= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, tx_delay / 500);
22 phy_modify(phydev, MDIO_DEVAD_NONE, XWAY_MDIO_MIICTRL,
23 XWAY_MDIO_MIICTRL_TXSKEW_MASK |
24 XWAY_MDIO_MIICTRL_RXSKEW_MASK, val);
25 }
26
27 genphy_config_aneg(phydev);
28
29 return 0;
30 }
31
32 U_BOOT_PHY_DRIVER(xway) = {
33 .name = "XWAY",
34 .uid = 0xD565A400,
35 .mask = 0xffffff00,
36 .features = PHY_GBIT_FEATURES,
37 .config = xway_config,
38 .startup = genphy_startup,
39 .shutdown = genphy_shutdown,
40 };
41