1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * RealTek PHY drivers
4 *
5 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
6 * author Andy Fleming
7 * Copyright 2016 Karsten Merker <merker@debian.org>
8 */
9 #include <linux/bitops.h>
10 #include <phy.h>
11 #include <linux/delay.h>
12
13 #define PHY_RTL8211x_FORCE_MASTER BIT(1)
14 #define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
15 #define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4)
16
17 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
18
19 /* RTL8211x 1000BASE-T Control Register */
20 #define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
21 #define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
22
23 /* RTL8211x PHY Status Register */
24 #define MIIM_RTL8211x_PHY_STATUS 0x11
25 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
26 #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
27 #define MIIM_RTL8211x_PHYSTAT_100 0x4000
28 #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
29 #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
30 #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
31
32 /* RTL8211x PHY Interrupt Enable Register */
33 #define MIIM_RTL8211x_PHY_INER 0x12
34 #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
35 #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
36
37 /* RTL8211x PHY Interrupt Status Register */
38 #define MIIM_RTL8211x_PHY_INSR 0x13
39
40 /* RTL8211F PHY Status Register */
41 #define MIIM_RTL8211F_PHY_STATUS 0x1a
42 #define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
43 #define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
44 #define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
45 #define MIIM_RTL8211F_PHYSTAT_100 0x0010
46 #define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
47 #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
48 #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
49
50 #define MIIM_RTL8211E_CONFREG 0x1c
51 #define MIIM_RTL8211E_CTRL_DELAY BIT(13)
52 #define MIIM_RTL8211E_TX_DELAY BIT(12)
53 #define MIIM_RTL8211E_RX_DELAY BIT(11)
54
55 #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
56
57 #define MIIM_RTL8211F_PAGE_SELECT 0x1f
58 #define MIIM_RTL8211F_TX_DELAY 0x100
59 #define MIIM_RTL8211F_RX_DELAY 0x8
60 #define MIIM_RTL8211F_LCR 0x10
61
62 #define RTL8201F_RMSR 0x10
63
64 #define RMSR_RX_TIMING_SHIFT BIT(2)
65 #define RMSR_RX_TIMING_MASK GENMASK(7, 4)
66 #define RMSR_RX_TIMING_VAL 0x4
67 #define RMSR_TX_TIMING_SHIFT BIT(3)
68 #define RMSR_TX_TIMING_MASK GENMASK(11, 8)
69 #define RMSR_TX_TIMING_VAL 0x5
70
rtl8211f_phy_extread(struct phy_device * phydev,int addr,int devaddr,int regnum)71 static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
72 int devaddr, int regnum)
73 {
74 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
75 MIIM_RTL8211F_PAGE_SELECT);
76 int val;
77
78 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
79 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
80 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
81
82 return val;
83 }
84
rtl8211f_phy_extwrite(struct phy_device * phydev,int addr,int devaddr,int regnum,u16 val)85 static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
86 int devaddr, int regnum, u16 val)
87 {
88 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
89 MIIM_RTL8211F_PAGE_SELECT);
90
91 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
92 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
93 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
94
95 return 0;
96 }
97
rtl8211b_probe(struct phy_device * phydev)98 static int rtl8211b_probe(struct phy_device *phydev)
99 {
100 #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
101 phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
102 #endif
103
104 return 0;
105 }
106
rtl8211e_probe(struct phy_device * phydev)107 static int rtl8211e_probe(struct phy_device *phydev)
108 {
109 return 0;
110 }
111
rtl8211f_probe(struct phy_device * phydev)112 static int rtl8211f_probe(struct phy_device *phydev)
113 {
114 #ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
115 phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
116 #endif
117
118 return 0;
119 }
120
rtl8210f_probe(struct phy_device * phydev)121 static int rtl8210f_probe(struct phy_device *phydev)
122 {
123 #ifdef CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS
124 phydev->flags |= PHY_RTL8201F_S700_RMII_TIMINGS;
125 #endif
126
127 return 0;
128 }
129
130 /* RealTek RTL8211x */
rtl8211x_config(struct phy_device * phydev)131 static int rtl8211x_config(struct phy_device *phydev)
132 {
133 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
134
135 /* mask interrupt at init; if the interrupt is
136 * needed indeed, it should be explicitly enabled
137 */
138 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
139 MIIM_RTL8211x_PHY_INTR_DIS);
140
141 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
142 unsigned int reg;
143
144 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
145 /* force manual master/slave configuration */
146 reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
147 /* force master mode */
148 reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
149 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
150 }
151 /* read interrupt status just to clear it */
152 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
153
154 genphy_config_aneg(phydev);
155
156 return 0;
157 }
158
159 /* RealTek RTL8201F */
rtl8201f_config(struct phy_device * phydev)160 static int rtl8201f_config(struct phy_device *phydev)
161 {
162 unsigned int reg;
163
164 if (phydev->flags & PHY_RTL8201F_S700_RMII_TIMINGS) {
165 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
166 7);
167 reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR);
168 reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK);
169 /* Set the needed Rx/Tx Timings for proper PHY operation */
170 reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT)
171 | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT);
172 phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);
173 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
174 0);
175 }
176
177 genphy_config_aneg(phydev);
178
179 return 0;
180 }
181
rtl8211e_config(struct phy_device * phydev)182 static int rtl8211e_config(struct phy_device *phydev)
183 {
184 int reg, val;
185
186 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
187 switch (phydev->interface) {
188 case PHY_INTERFACE_MODE_RGMII:
189 val = MIIM_RTL8211E_CTRL_DELAY;
190 break;
191 case PHY_INTERFACE_MODE_RGMII_ID:
192 val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY |
193 MIIM_RTL8211E_RX_DELAY;
194 break;
195 case PHY_INTERFACE_MODE_RGMII_RXID:
196 val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_RX_DELAY;
197 break;
198 case PHY_INTERFACE_MODE_RGMII_TXID:
199 val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY;
200 break;
201 default: /* the rest of the modes imply leaving delays as is. */
202 goto default_delay;
203 }
204
205 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 7);
206 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
207
208 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
209 reg &= ~(MIIM_RTL8211E_TX_DELAY | MIIM_RTL8211E_RX_DELAY);
210 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg | val);
211
212 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0);
213
214 default_delay:
215 genphy_config_aneg(phydev);
216
217 return 0;
218 }
219
rtl8211f_config(struct phy_device * phydev)220 static int rtl8211f_config(struct phy_device *phydev)
221 {
222 u16 reg;
223
224 if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
225 unsigned int reg;
226
227 reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
228 reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
229 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
230 }
231
232 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
233
234 phy_write(phydev, MDIO_DEVAD_NONE,
235 MIIM_RTL8211F_PAGE_SELECT, 0xd08);
236 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
237
238 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
239 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
240 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
241 reg |= MIIM_RTL8211F_TX_DELAY;
242 else
243 reg &= ~MIIM_RTL8211F_TX_DELAY;
244
245 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
246
247 /* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
248 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
249 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
250 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
251 reg |= MIIM_RTL8211F_RX_DELAY;
252 else
253 reg &= ~MIIM_RTL8211F_RX_DELAY;
254 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
255
256 /* restore to default page 0 */
257 phy_write(phydev, MDIO_DEVAD_NONE,
258 MIIM_RTL8211F_PAGE_SELECT, 0x0);
259
260 /* Set green LED for Link, yellow LED for Active */
261 phy_write(phydev, MDIO_DEVAD_NONE,
262 MIIM_RTL8211F_PAGE_SELECT, 0xd04);
263 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
264 phy_write(phydev, MDIO_DEVAD_NONE,
265 MIIM_RTL8211F_PAGE_SELECT, 0x0);
266
267 genphy_config_aneg(phydev);
268
269 return 0;
270 }
271
rtl8211x_parse_status(struct phy_device * phydev)272 static int rtl8211x_parse_status(struct phy_device *phydev)
273 {
274 unsigned int speed;
275 unsigned int mii_reg;
276
277 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
278
279 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
280 int i = 0;
281
282 /* in case of timeout ->link is cleared */
283 phydev->link = 1;
284 puts("Waiting for PHY realtime link");
285 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
286 /* Timeout reached ? */
287 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
288 puts(" TIMEOUT !\n");
289 phydev->link = 0;
290 break;
291 }
292
293 if ((i++ % 1000) == 0)
294 putc('.');
295 udelay(1000); /* 1 ms */
296 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
297 MIIM_RTL8211x_PHY_STATUS);
298 }
299 puts(" done\n");
300 udelay(500000); /* another 500 ms (results in faster booting) */
301 } else {
302 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
303 phydev->link = 1;
304 else
305 phydev->link = 0;
306 }
307
308 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
309 phydev->duplex = DUPLEX_FULL;
310 else
311 phydev->duplex = DUPLEX_HALF;
312
313 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
314
315 switch (speed) {
316 case MIIM_RTL8211x_PHYSTAT_GBIT:
317 phydev->speed = SPEED_1000;
318 break;
319 case MIIM_RTL8211x_PHYSTAT_100:
320 phydev->speed = SPEED_100;
321 break;
322 default:
323 phydev->speed = SPEED_10;
324 }
325
326 return 0;
327 }
328
rtl8211f_parse_status(struct phy_device * phydev)329 static int rtl8211f_parse_status(struct phy_device *phydev)
330 {
331 unsigned int speed;
332 unsigned int mii_reg;
333 int i = 0;
334
335 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
336 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
337
338 phydev->link = 1;
339 while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
340 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
341 puts(" TIMEOUT !\n");
342 phydev->link = 0;
343 break;
344 }
345
346 if ((i++ % 1000) == 0)
347 putc('.');
348 udelay(1000);
349 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
350 MIIM_RTL8211F_PHY_STATUS);
351 }
352
353 if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
354 phydev->duplex = DUPLEX_FULL;
355 else
356 phydev->duplex = DUPLEX_HALF;
357
358 speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
359
360 switch (speed) {
361 case MIIM_RTL8211F_PHYSTAT_GBIT:
362 phydev->speed = SPEED_1000;
363 break;
364 case MIIM_RTL8211F_PHYSTAT_100:
365 phydev->speed = SPEED_100;
366 break;
367 default:
368 phydev->speed = SPEED_10;
369 }
370
371 return 0;
372 }
373
rtl8211x_startup(struct phy_device * phydev)374 static int rtl8211x_startup(struct phy_device *phydev)
375 {
376 int ret;
377
378 /* Read the Status (2x to make sure link is right) */
379 ret = genphy_update_link(phydev);
380 if (ret)
381 return ret;
382
383 return rtl8211x_parse_status(phydev);
384 }
385
rtl8211f_startup(struct phy_device * phydev)386 static int rtl8211f_startup(struct phy_device *phydev)
387 {
388 int ret;
389
390 /* Read the Status (2x to make sure link is right) */
391 ret = genphy_update_link(phydev);
392 if (ret)
393 return ret;
394 /* Read the Status (2x to make sure link is right) */
395
396 return rtl8211f_parse_status(phydev);
397 }
398
399 /* Support for RTL8211B PHY */
400 U_BOOT_PHY_DRIVER(rtl8211b) = {
401 .name = "RealTek RTL8211B",
402 .uid = 0x1cc912,
403 .mask = 0xffffff,
404 .features = PHY_GBIT_FEATURES,
405 .probe = &rtl8211b_probe,
406 .config = &rtl8211x_config,
407 .startup = &rtl8211x_startup,
408 .shutdown = &genphy_shutdown,
409 };
410
411 /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
412 U_BOOT_PHY_DRIVER(rtl8211e) = {
413 .name = "RealTek RTL8211E",
414 .uid = 0x1cc915,
415 .mask = 0xffffff,
416 .features = PHY_GBIT_FEATURES,
417 .probe = &rtl8211e_probe,
418 .config = &rtl8211e_config,
419 .startup = &genphy_startup,
420 .shutdown = &genphy_shutdown,
421 };
422
423 /* Support for RTL8211DN PHY */
424 U_BOOT_PHY_DRIVER(rtl8211dn) = {
425 .name = "RealTek RTL8211DN",
426 .uid = 0x1cc914,
427 .mask = 0xffffff,
428 .features = PHY_GBIT_FEATURES,
429 .config = &rtl8211x_config,
430 .startup = &rtl8211x_startup,
431 .shutdown = &genphy_shutdown,
432 };
433
434 /* Support for RTL8211F PHY */
435 U_BOOT_PHY_DRIVER(rtl8211f) = {
436 .name = "RealTek RTL8211F",
437 .uid = 0x1cc916,
438 .mask = 0xffffff,
439 .features = PHY_GBIT_FEATURES,
440 .probe = &rtl8211f_probe,
441 .config = &rtl8211f_config,
442 .startup = &rtl8211f_startup,
443 .shutdown = &genphy_shutdown,
444 .readext = &rtl8211f_phy_extread,
445 .writeext = &rtl8211f_phy_extwrite,
446 };
447
448 /* Support for RTL8211F-VD PHY */
449 U_BOOT_PHY_DRIVER(rtl8211fvd) = {
450 .name = "RealTek RTL8211F-VD",
451 .uid = 0x1cc878,
452 .mask = 0xffffff,
453 .features = PHY_GBIT_FEATURES,
454 .probe = &rtl8211f_probe,
455 .config = &rtl8211f_config,
456 .startup = &rtl8211f_startup,
457 .shutdown = &genphy_shutdown,
458 .readext = &rtl8211f_phy_extread,
459 .writeext = &rtl8211f_phy_extwrite,
460 };
461
462 /* Support for RTL8201F PHY */
463 U_BOOT_PHY_DRIVER(rtl8201f) = {
464 .name = "RealTek RTL8201F 10/100Mbps Ethernet",
465 .uid = 0x1cc816,
466 .mask = 0xffffff,
467 .features = PHY_BASIC_FEATURES,
468 .probe = &rtl8210f_probe,
469 .config = &rtl8201f_config,
470 .startup = &genphy_startup,
471 .shutdown = &genphy_shutdown,
472 };
473