1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
4 *
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 *
7 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
8 * follows:
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * dm644x_emac.c
13 *
14 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
15 *
16 * Copyright (C) 2005 Texas Instruments.
17 *
18 * ----------------------------------------------------------------------------
19 *
20 * Modifications:
21 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
22 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
23 */
24 #include <config.h>
25 #include <command.h>
26 #include <cpu_func.h>
27 #include <log.h>
28 #include <net.h>
29 #include <miiphy.h>
30 #include <malloc.h>
31 #include <asm/cache.h>
32 #include <linux/compiler.h>
33 #include <asm/arch/emac_defs.h>
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include "davinci_emac.h"
37
38 unsigned int emac_dbg = 0;
39 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
40
41 #ifdef EMAC_HW_RAM_ADDR
BD_TO_HW(unsigned long x)42 static inline unsigned long BD_TO_HW(unsigned long x)
43 {
44 if (x == 0)
45 return 0;
46
47 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
48 }
49
HW_TO_BD(unsigned long x)50 static inline unsigned long HW_TO_BD(unsigned long x)
51 {
52 if (x == 0)
53 return 0;
54
55 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
56 }
57 #else
58 #define BD_TO_HW(x) (x)
59 #define HW_TO_BD(x) (x)
60 #endif
61
62 #ifdef DAVINCI_EMAC_GIG_ENABLE
63 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
64 #else
65 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
66 #endif
67
68 #if !defined(CFG_SYS_EMAC_TI_CLKDIV)
69 #define CFG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
70 EMAC_MDIO_CLOCK_FREQ) - 1)
71 #endif
72
73 static void davinci_eth_mdio_enable(void);
74
75 static int gen_init_phy(int phy_addr);
76 static int gen_is_phy_connected(int phy_addr);
77 static int gen_get_link_speed(int phy_addr);
78 static int gen_auto_negotiate(int phy_addr);
79
eth_mdio_enable(void)80 void eth_mdio_enable(void)
81 {
82 davinci_eth_mdio_enable();
83 }
84
85 /* EMAC Addresses */
86 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
87 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
88 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
89
90 /* EMAC descriptors */
91 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
92 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
93 static volatile emac_desc *emac_rx_active_head = 0;
94 static volatile emac_desc *emac_rx_active_tail = 0;
95 static int emac_rx_queue_active = 0;
96
97 /* Receive packet buffers */
98 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
99 __aligned(ARCH_DMA_MINALIGN);
100
101 #ifndef CFG_SYS_DAVINCI_EMAC_PHY_COUNT
102 #define CFG_SYS_DAVINCI_EMAC_PHY_COUNT 3
103 #endif
104
105 /* PHY address for a discovered PHY (0xff - not found) */
106 static u_int8_t active_phy_addr[CFG_SYS_DAVINCI_EMAC_PHY_COUNT];
107
108 /* number of PHY found active */
109 static u_int8_t num_phy;
110
111 phy_t phy[CFG_SYS_DAVINCI_EMAC_PHY_COUNT];
112
davinci_emac_write_hwaddr(struct udevice * dev)113 static int davinci_emac_write_hwaddr(struct udevice *dev)
114 {
115 struct eth_pdata *pdata = dev_get_plat(dev);
116 unsigned long mac_hi;
117 unsigned long mac_lo;
118
119 /*
120 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
121 * receive)
122 * Using channel 0 only - other channels are disabled
123 * */
124 writel(0, &adap_emac->MACINDEX);
125 mac_hi = (pdata->enetaddr[3] << 24) |
126 (pdata->enetaddr[2] << 16) |
127 (pdata->enetaddr[1] << 8) |
128 (pdata->enetaddr[0]);
129 mac_lo = (pdata->enetaddr[5] << 8) |
130 (pdata->enetaddr[4]);
131
132 writel(mac_hi, &adap_emac->MACADDRHI);
133 #if defined(DAVINCI_EMAC_VERSION2)
134 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
135 &adap_emac->MACADDRLO);
136 #else
137 writel(mac_lo, &adap_emac->MACADDRLO);
138 #endif
139
140 writel(0, &adap_emac->MACHASH1);
141 writel(0, &adap_emac->MACHASH2);
142
143 /* Set source MAC address - REQUIRED */
144 writel(mac_hi, &adap_emac->MACSRCADDRHI);
145 writel(mac_lo, &adap_emac->MACSRCADDRLO);
146
147 return 0;
148 }
149
davinci_eth_mdio_enable(void)150 static void davinci_eth_mdio_enable(void)
151 {
152 u_int32_t clkdiv;
153
154 clkdiv = CFG_SYS_EMAC_TI_CLKDIV;
155
156 writel((clkdiv & 0xff) |
157 MDIO_CONTROL_ENABLE |
158 MDIO_CONTROL_FAULT |
159 MDIO_CONTROL_FAULT_ENABLE,
160 &adap_mdio->CONTROL);
161
162 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
163 ;
164 }
165
166 /*
167 * Tries to find an active connected PHY. Returns 1 if address if found.
168 * If no active PHY (or more than one PHY) found returns 0.
169 * Sets active_phy_addr variable.
170 */
davinci_eth_phy_detect(void)171 static int davinci_eth_phy_detect(void)
172 {
173 u_int32_t phy_act_state;
174 int i;
175 int j;
176 unsigned int count = 0;
177
178 for (i = 0; i < CFG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
179 active_phy_addr[i] = 0xff;
180
181 udelay(1000);
182 phy_act_state = readl(&adap_mdio->ALIVE);
183
184 if (phy_act_state == 0)
185 return 0; /* No active PHYs */
186
187 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
188
189 for (i = 0, j = 0; i < 32; i++)
190 if (phy_act_state & (1 << i)) {
191 count++;
192 if (count <= CFG_SYS_DAVINCI_EMAC_PHY_COUNT) {
193 active_phy_addr[j++] = i;
194 } else {
195 printf("%s: to many PHYs detected.\n",
196 __func__);
197 count = 0;
198 break;
199 }
200 }
201
202 num_phy = count;
203
204 return count;
205 }
206
207 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
davinci_eth_phy_read(u_int8_t phy_addr,u_int8_t reg_num,u_int16_t * data)208 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
209 {
210 int tmp;
211
212 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
213 ;
214
215 writel(MDIO_USERACCESS0_GO |
216 MDIO_USERACCESS0_WRITE_READ |
217 ((reg_num & 0x1f) << 21) |
218 ((phy_addr & 0x1f) << 16),
219 &adap_mdio->USERACCESS0);
220
221 /* Wait for command to complete */
222 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
223 ;
224
225 if (tmp & MDIO_USERACCESS0_ACK) {
226 *data = tmp & 0xffff;
227 return 1;
228 }
229
230 return 0;
231 }
232
233 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
davinci_eth_phy_write(u_int8_t phy_addr,u_int8_t reg_num,u_int16_t data)234 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
235 {
236
237 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
238 ;
239
240 writel(MDIO_USERACCESS0_GO |
241 MDIO_USERACCESS0_WRITE_WRITE |
242 ((reg_num & 0x1f) << 21) |
243 ((phy_addr & 0x1f) << 16) |
244 (data & 0xffff),
245 &adap_mdio->USERACCESS0);
246
247 /* Wait for command to complete */
248 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
249 ;
250
251 return 1;
252 }
253
254 /* PHY functions for a generic PHY */
gen_init_phy(int phy_addr)255 static int gen_init_phy(int phy_addr)
256 {
257 int ret = 1;
258
259 if (gen_get_link_speed(phy_addr)) {
260 /* Try another time */
261 ret = gen_get_link_speed(phy_addr);
262 }
263
264 return(ret);
265 }
266
gen_is_phy_connected(int phy_addr)267 static int gen_is_phy_connected(int phy_addr)
268 {
269 u_int16_t dummy;
270
271 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
272 }
273
get_active_phy(void)274 static int get_active_phy(void)
275 {
276 int i;
277
278 for (i = 0; i < num_phy; i++)
279 if (phy[i].get_link_speed(active_phy_addr[i]))
280 return i;
281
282 return -1; /* Return error if no link */
283 }
284
gen_get_link_speed(int phy_addr)285 static int gen_get_link_speed(int phy_addr)
286 {
287 u_int16_t tmp;
288
289 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
290 (tmp & 0x04)) {
291 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
292 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
293 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
294
295 /* Speed doesn't matter, there is no setting for it in EMAC. */
296 if (tmp & (LPA_100FULL | LPA_10FULL)) {
297 /* set EMAC for Full Duplex */
298 writel(EMAC_MACCONTROL_MIIEN_ENABLE |
299 EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
300 &adap_emac->MACCONTROL);
301 } else {
302 /*set EMAC for Half Duplex */
303 writel(EMAC_MACCONTROL_MIIEN_ENABLE,
304 &adap_emac->MACCONTROL);
305 }
306
307 if (tmp & (LPA_100FULL | LPA_100HALF))
308 writel(readl(&adap_emac->MACCONTROL) |
309 EMAC_MACCONTROL_RMIISPEED_100,
310 &adap_emac->MACCONTROL);
311 else
312 writel(readl(&adap_emac->MACCONTROL) &
313 ~EMAC_MACCONTROL_RMIISPEED_100,
314 &adap_emac->MACCONTROL);
315 #endif
316 return(1);
317 }
318
319 return(0);
320 }
321
gen_auto_negotiate(int phy_addr)322 static int gen_auto_negotiate(int phy_addr)
323 {
324 u_int16_t tmp;
325 u_int16_t val;
326 unsigned long cntr = 0;
327
328 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
329 return 0;
330
331 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
332 BMCR_SPEED100;
333 davinci_eth_phy_write(phy_addr, MII_BMCR, val);
334
335 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
336 return 0;
337
338 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
339 ADVERTISE_10HALF);
340 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
341
342 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
343 return(0);
344
345 #ifdef DAVINCI_EMAC_GIG_ENABLE
346 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
347 val |= PHY_1000BTCR_1000FD;
348 val &= ~PHY_1000BTCR_1000HD;
349 davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
350 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
351 #endif
352
353 /* Restart Auto_negotiation */
354 tmp |= BMCR_ANRESTART;
355 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
356
357 /*check AutoNegotiate complete */
358 do {
359 udelay(40000);
360 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
361 return 0;
362
363 if (tmp & BMSR_ANEGCOMPLETE)
364 break;
365
366 cntr++;
367 } while (cntr < 200);
368
369 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
370 return(0);
371
372 if (!(tmp & BMSR_ANEGCOMPLETE))
373 return(0);
374
375 return(gen_get_link_speed(phy_addr));
376 }
377 /* End of generic PHY functions */
378
379 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
davinci_mii_phy_read(struct mii_dev * bus,int addr,int devad,int reg)380 static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
381 int reg)
382 {
383 unsigned short value = 0;
384 int retval = davinci_eth_phy_read(addr, reg, &value);
385
386 return retval ? value : -EIO;
387 }
388
davinci_mii_phy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)389 static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
390 int reg, u16 value)
391 {
392 return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
393 }
394 #endif
395
davinci_eth_gigabit_enable(int phy_addr)396 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
397 {
398 u_int16_t data;
399
400 if (davinci_eth_phy_read(phy_addr, 0, &data)) {
401 if (data & (1 << 6)) { /* speed selection MSB */
402 /*
403 * Check if link detected is giga-bit
404 * If Gigabit mode detected, enable gigbit in MAC
405 */
406 writel(readl(&adap_emac->MACCONTROL) |
407 EMAC_MACCONTROL_GIGFORCE |
408 EMAC_MACCONTROL_GIGABIT_ENABLE,
409 &adap_emac->MACCONTROL);
410 }
411 }
412 }
413
414 /* Eth device open */
davinci_emac_start(struct udevice * dev)415 static int davinci_emac_start(struct udevice *dev)
416 {
417 dv_reg_p addr;
418 u_int32_t clkdiv, cnt, mac_control;
419 uint16_t __maybe_unused lpa_val;
420 volatile emac_desc *rx_desc;
421 int index;
422
423 debug_emac("+ emac_open\n");
424
425 /* Reset EMAC module and disable interrupts in wrapper */
426 writel(1, &adap_emac->SOFTRESET);
427 while (readl(&adap_emac->SOFTRESET) != 0)
428 ;
429 #if defined(DAVINCI_EMAC_VERSION2)
430 writel(1, &adap_ewrap->softrst);
431 while (readl(&adap_ewrap->softrst) != 0)
432 ;
433 #else
434 writel(0, &adap_ewrap->EWCTL);
435 for (cnt = 0; cnt < 5; cnt++) {
436 clkdiv = readl(&adap_ewrap->EWCTL);
437 }
438 #endif
439
440 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
441 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
442 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
443 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
444 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
445 #endif
446 rx_desc = emac_rx_desc;
447
448 writel(1, &adap_emac->TXCONTROL);
449 writel(1, &adap_emac->RXCONTROL);
450
451 davinci_emac_write_hwaddr(dev);
452
453 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
454 addr = &adap_emac->TX0HDP;
455 for (cnt = 0; cnt < 8; cnt++)
456 writel(0, addr++);
457
458 addr = &adap_emac->RX0HDP;
459 for (cnt = 0; cnt < 8; cnt++)
460 writel(0, addr++);
461
462 /* Clear Statistics (do this before setting MacControl register) */
463 addr = &adap_emac->RXGOODFRAMES;
464 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
465 writel(0, addr++);
466
467 /* No multicast addressing */
468 writel(0, &adap_emac->MACHASH1);
469 writel(0, &adap_emac->MACHASH2);
470
471 /* Create RX queue and set receive process in place */
472 emac_rx_active_head = emac_rx_desc;
473 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
474 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
475 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
476 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
477 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
478 rx_desc++;
479 }
480
481 /* Finalize the rx desc list */
482 rx_desc--;
483 rx_desc->next = 0;
484 emac_rx_active_tail = rx_desc;
485 emac_rx_queue_active = 1;
486
487 /* Enable TX/RX */
488 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
489 writel(0, &adap_emac->RXBUFFEROFFSET);
490
491 /*
492 * No fancy configs - Use this for promiscous debug
493 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
494 */
495 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
496
497 /* Enable ch 0 only */
498 writel(1, &adap_emac->RXUNICASTSET);
499
500 /* Init MDIO & get link state */
501 clkdiv = CFG_SYS_EMAC_TI_CLKDIV;
502 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
503 &adap_mdio->CONTROL);
504
505 /* We need to wait for MDIO to start */
506 udelay(1000);
507
508 index = get_active_phy();
509 if (index == -1)
510 return(0);
511
512 /* Enable MII interface */
513 mac_control = EMAC_MACCONTROL_MIIEN_ENABLE;
514 #ifdef DAVINCI_EMAC_GIG_ENABLE
515 davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val);
516 if (lpa_val & PHY_1000BTSR_1000FD) {
517 debug_emac("eth_open : gigabit negotiated\n");
518 mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
519 mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE;
520 }
521 #endif
522
523 davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val);
524 if (lpa_val & (LPA_100FULL | LPA_10FULL))
525 /* set EMAC for Full Duplex */
526 mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
527 #if defined(CONFIG_SOC_DA8XX) || \
528 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
529 mac_control |= EMAC_MACCONTROL_RMIISPEED_100;
530 #endif
531 writel(mac_control, &adap_emac->MACCONTROL);
532 /* Start receive process */
533 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
534
535 debug_emac("- emac_open\n");
536
537 return(1);
538 }
539
540 /* EMAC Channel Teardown */
davinci_eth_ch_teardown(int ch)541 static void davinci_eth_ch_teardown(int ch)
542 {
543 dv_reg dly = 0xff;
544 dv_reg cnt;
545
546 debug_emac("+ emac_ch_teardown\n");
547
548 if (ch == EMAC_CH_TX) {
549 /* Init TX channel teardown */
550 writel(0, &adap_emac->TXTEARDOWN);
551 do {
552 /*
553 * Wait here for Tx teardown completion interrupt to
554 * occur. Note: A task delay can be called here to pend
555 * rather than occupying CPU cycles - anyway it has
556 * been found that teardown takes very few cpu cycles
557 * and does not affect functionality
558 */
559 dly--;
560 udelay(1);
561 if (dly == 0)
562 break;
563 cnt = readl(&adap_emac->TX0CP);
564 } while (cnt != 0xfffffffc);
565 writel(cnt, &adap_emac->TX0CP);
566 writel(0, &adap_emac->TX0HDP);
567 } else {
568 /* Init RX channel teardown */
569 writel(0, &adap_emac->RXTEARDOWN);
570 do {
571 /*
572 * Wait here for Rx teardown completion interrupt to
573 * occur. Note: A task delay can be called here to pend
574 * rather than occupying CPU cycles - anyway it has
575 * been found that teardown takes very few cpu cycles
576 * and does not affect functionality
577 */
578 dly--;
579 udelay(1);
580 if (dly == 0)
581 break;
582 cnt = readl(&adap_emac->RX0CP);
583 } while (cnt != 0xfffffffc);
584 writel(cnt, &adap_emac->RX0CP);
585 writel(0, &adap_emac->RX0HDP);
586 }
587
588 debug_emac("- emac_ch_teardown\n");
589 }
590
591 /* Eth device close */
davinci_emac_stop(struct udevice * dev)592 static void davinci_emac_stop(struct udevice *dev)
593 {
594 debug_emac("+ emac_close\n");
595
596 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
597 if (readl(&adap_emac->RXCONTROL) & 1)
598 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
599
600 /* Reset EMAC module and disable interrupts in wrapper */
601 writel(1, &adap_emac->SOFTRESET);
602 #if defined(DAVINCI_EMAC_VERSION2)
603 writel(1, &adap_ewrap->softrst);
604 #else
605 writel(0, &adap_ewrap->EWCTL);
606 #endif
607
608 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
609 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
610 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
611 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
612 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
613 #endif
614 debug_emac("- emac_close\n");
615 }
616
617 static int tx_send_loop = 0;
618
619 /*
620 * This function sends a single packet on the network and returns
621 * positive number (number of bytes transmitted) or negative for error
622 */
davinci_emac_send(struct udevice * dev,void * packet,int length)623 static int davinci_emac_send(struct udevice *dev,
624 void *packet, int length)
625 {
626 int ret_status = -1;
627 int index;
628 tx_send_loop = 0;
629
630 index = get_active_phy();
631 if (index == -1) {
632 printf(" WARN: emac_send_packet: No link\n");
633 return (ret_status);
634 }
635
636 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
637 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
638 length = EMAC_MIN_ETHERNET_PKT_SIZE;
639 }
640
641 /* Populate the TX descriptor */
642 emac_tx_desc->next = 0;
643 emac_tx_desc->buffer = (u_int8_t *) packet;
644 emac_tx_desc->buff_off_len = (length & 0xffff);
645 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
646 EMAC_CPPI_SOP_BIT |
647 EMAC_CPPI_OWNERSHIP_BIT |
648 EMAC_CPPI_EOP_BIT);
649
650 flush_dcache_range((unsigned long)packet,
651 (unsigned long)packet + ALIGN(length, PKTALIGN));
652
653 /* Send the packet */
654 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
655
656 /* Wait for packet to complete or link down */
657 while (1) {
658 if (!phy[index].get_link_speed(active_phy_addr[index])) {
659 davinci_eth_ch_teardown (EMAC_CH_TX);
660 return (ret_status);
661 }
662
663 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
664 ret_status = length;
665 break;
666 }
667 tx_send_loop++;
668 }
669
670 return (ret_status);
671 }
672
673 /*
674 * This function handles receipt of a packet from the network
675 */
davinci_emac_recv(struct udevice * dev,int flags,uchar ** packetp)676 static int davinci_emac_recv(struct udevice *dev, int flags, uchar **packetp)
677 {
678 volatile emac_desc *rx_curr_desc;
679 volatile emac_desc *curr_desc;
680 volatile emac_desc *tail_desc;
681 int status, ret = -1;
682
683 rx_curr_desc = emac_rx_active_head;
684 if (!rx_curr_desc)
685 return 0;
686 *packetp = rx_curr_desc->buffer;
687 status = rx_curr_desc->pkt_flag_len;
688 if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
689 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
690 /* Error in packet - discard it and requeue desc */
691 printf ("WARN: emac_rcv_pkt: Error in packet\n");
692 } else {
693 unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
694 unsigned short len =
695 rx_curr_desc->buff_off_len & 0xffff;
696
697 invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
698 ret = len;
699 }
700
701 /* Ack received packet descriptor */
702 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
703 curr_desc = rx_curr_desc;
704 emac_rx_active_head =
705 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
706
707 if (status & EMAC_CPPI_EOQ_BIT) {
708 if (emac_rx_active_head) {
709 writel(BD_TO_HW((ulong)emac_rx_active_head),
710 &adap_emac->RX0HDP);
711 } else {
712 emac_rx_queue_active = 0;
713 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
714 }
715 }
716
717 /* Recycle RX descriptor */
718 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
719 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
720 rx_curr_desc->next = 0;
721
722 if (emac_rx_active_head == 0) {
723 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
724 emac_rx_active_head = curr_desc;
725 emac_rx_active_tail = curr_desc;
726 if (emac_rx_queue_active != 0) {
727 writel(BD_TO_HW((ulong)emac_rx_active_head),
728 &adap_emac->RX0HDP);
729 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
730 emac_rx_queue_active = 1;
731 }
732 } else {
733 tail_desc = emac_rx_active_tail;
734 emac_rx_active_tail = curr_desc;
735 tail_desc->next = BD_TO_HW((ulong) curr_desc);
736 status = tail_desc->pkt_flag_len;
737 if (status & EMAC_CPPI_EOQ_BIT) {
738 writel(BD_TO_HW((ulong)curr_desc),
739 &adap_emac->RX0HDP);
740 status &= ~EMAC_CPPI_EOQ_BIT;
741 tail_desc->pkt_flag_len = status;
742 }
743 }
744 return (ret);
745 }
746
747 return (0);
748 }
749
750 /*
751 * This function initializes the emac hardware. It does NOT initialize
752 * EMAC modules power or pin multiplexors, that is done by board_init()
753 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
754 */
davinci_emac_probe(struct udevice * dev)755 static int davinci_emac_probe(struct udevice *dev)
756 {
757 u_int32_t phy_id;
758 u_int16_t tmp;
759 int i;
760 int ret;
761
762 davinci_eth_mdio_enable();
763
764 /* let the EMAC detect the PHYs */
765 udelay(5000);
766
767 for (i = 0; i < 256; i++) {
768 if (readl(&adap_mdio->ALIVE))
769 break;
770 udelay(1000);
771 }
772
773 if (i >= 256) {
774 printf("No ETH PHY detected!!!\n");
775 return(0);
776 }
777
778 /* Find if PHY(s) is/are connected */
779 ret = davinci_eth_phy_detect();
780 if (!ret)
781 return(0);
782 else
783 debug_emac(" %d ETH PHY detected\n", ret);
784
785 /* Get PHY ID and initialize phy_ops for a detected PHY */
786 for (i = 0; i < num_phy; i++) {
787 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
788 &tmp)) {
789 active_phy_addr[i] = 0xff;
790 continue;
791 }
792
793 phy_id = (tmp << 16) & 0xffff0000;
794
795 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
796 &tmp)) {
797 active_phy_addr[i] = 0xff;
798 continue;
799 }
800
801 phy_id |= tmp & 0x0000ffff;
802
803 sprintf(phy[i].name, "GENERIC @ 0x%02x",
804 active_phy_addr[i]);
805 phy[i].init = gen_init_phy;
806 phy[i].is_phy_connected = gen_is_phy_connected;
807 phy[i].get_link_speed = gen_get_link_speed;
808 phy[i].auto_negotiate = gen_auto_negotiate;
809
810 debug("Ethernet PHY: %s\n", phy[i].name);
811
812 int retval;
813 struct mii_dev *mdiodev = mdio_alloc();
814 if (!mdiodev)
815 return -ENOMEM;
816 strlcpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
817 mdiodev->read = davinci_mii_phy_read;
818 mdiodev->write = davinci_mii_phy_write;
819
820 retval = mdio_register(mdiodev);
821 if (retval < 0)
822 return retval;
823 #ifdef DAVINCI_EMAC_GIG_ENABLE
824 #define PHY_CONF_REG 22
825 /* Enable PHY to clock out TX_CLK */
826 davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
827 tmp |= PHY_CONF_TXCLKEN;
828 davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
829 davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
830 #endif
831 }
832
833 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
834 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
835 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
836 for (i = 0; i < num_phy; i++) {
837 if (phy[i].is_phy_connected(i))
838 phy[i].auto_negotiate(i);
839 }
840 #endif
841 return 0;
842 }
843
844 static const struct eth_ops davinci_emac_ops = {
845 .start = davinci_emac_start,
846 .send = davinci_emac_send,
847 .recv = davinci_emac_recv,
848 .stop = davinci_emac_stop,
849 .write_hwaddr = davinci_emac_write_hwaddr,
850 };
851
852 static const struct udevice_id davinci_emac_ids[] = {
853 { .compatible = "ti,davinci-dm6467-emac" },
854 { .compatible = "ti,am3517-emac", },
855 { .compatible = "ti,dm816-emac", },
856 { }
857 };
858
859 U_BOOT_DRIVER(davinci_emac) = {
860 .name = "davinci_emac",
861 .id = UCLASS_ETH,
862 .of_match = davinci_emac_ids,
863 .probe = davinci_emac_probe,
864 .ops = &davinci_emac_ops,
865 .plat_auto = sizeof(struct eth_pdata),
866 };
867