1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Google, Inc
4 */
5
6 #define LOG_CATEGORY UCLASS_PCH
7
8 #include <dm.h>
9 #include <log.h>
10 #include <pch.h>
11
12 #define GPIO_BASE 0x48
13 #define IO_BASE 0x4c
14 #define SBASE_ADDR 0x54
15
pch9_get_spi_base(struct udevice * dev,ulong * sbasep)16 static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
17 {
18 uint32_t sbase_addr;
19
20 dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
21 *sbasep = sbase_addr & 0xfffffe00;
22
23 return 0;
24 }
25
pch9_get_gpio_base(struct udevice * dev,u32 * gbasep)26 static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
27 {
28 u32 base;
29
30 /*
31 * GPIO_BASE moved to its current offset with ICH6, but prior to
32 * that it was unused (or undocumented). Check that it looks
33 * okay: not all ones or zeros.
34 *
35 * Note we don't need check bit0 here, because the Tunnel Creek
36 * GPIO base address register bit0 is reserved (read returns 0),
37 * while on the Ivybridge the bit0 is used to indicate it is an
38 * I/O space.
39 */
40 dm_pci_read_config32(dev, GPIO_BASE, &base);
41 if (base == 0x00000000 || base == 0xffffffff) {
42 log_debug("unexpected BASE value\n");
43 return -ENODEV;
44 }
45
46 /*
47 * Okay, I guess we're looking at the right device. The actual
48 * GPIO registers are in the PCI device's I/O space, starting
49 * at the offset that we just read. Bit 0 indicates that it's
50 * an I/O address, not a memory address, so mask that off.
51 */
52 *gbasep = base & 1 ? base & ~3 : base & ~15;
53
54 return 0;
55 }
56
pch9_get_io_base(struct udevice * dev,u32 * iobasep)57 static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
58 {
59 u32 base;
60
61 dm_pci_read_config32(dev, IO_BASE, &base);
62 if (base == 0x00000000 || base == 0xffffffff) {
63 log_debug("unexpected BASE value\n");
64 return -ENODEV;
65 }
66
67 *iobasep = base & 1 ? base & ~3 : base & ~15;
68
69 return 0;
70 }
71
72 static const struct pch_ops pch9_ops = {
73 .get_spi_base = pch9_get_spi_base,
74 .get_gpio_base = pch9_get_gpio_base,
75 .get_io_base = pch9_get_io_base,
76 };
77
78 static const struct udevice_id pch9_ids[] = {
79 { .compatible = "intel,pch9" },
80 { }
81 };
82
83 U_BOOT_DRIVER(pch9_drv) = {
84 .name = "intel-pch9",
85 .id = UCLASS_PCH,
86 .of_match = pch9_ids,
87 .ops = &pch9_ops,
88 };
89