1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015-2016 Marvell International Ltd.
4  */
5 
6 #ifndef _UTMI_PHY_H_
7 #define _UTMI_PHY_H_
8 
9 #define UTMI_USB_CFG_DEVICE_EN_OFFSET		0
10 #define UTMI_USB_CFG_DEVICE_EN_MASK		\
11 	(0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET)
12 #define UTMI_USB_CFG_DEVICE_MUX_OFFSET		1
13 #define UTMI_USB_CFG_DEVICE_MUX_MASK		\
14 	(0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET)
15 #define UTMI_USB_CFG_PLL_OFFSET			25
16 #define UTMI_USB_CFG_PLL_MASK			\
17 	(0x1 << UTMI_USB_CFG_PLL_OFFSET)
18 
19 #define UTMI_PHY_CFG_PU_OFFSET			5
20 #define UTMI_PHY_CFG_PU_MASK			\
21 	(0x1 << UTMI_PHY_CFG_PU_OFFSET)
22 
23 #define UTMI_PLL_CTRL_REG			0x0
24 #define UTMI_PLL_CTRL_REFDIV_OFFSET		0
25 #define UTMI_PLL_CTRL_REFDIV_MASK		\
26 	(0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET)
27 #define UTMI_PLL_CTRL_FBDIV_OFFSET		16
28 #define UTMI_PLL_CTRL_FBDIV_MASK		\
29 	(0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET)
30 #define UTMI_PLL_CTRL_SEL_LPFR_OFFSET		28
31 #define UTMI_PLL_CTRL_SEL_LPFR_MASK		\
32 	(0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET)
33 #define UTMI_PLL_CTRL_PLL_RDY_OFFSET		31
34 #define UTMI_PLL_CTRL_PLL_RDY_MASK		\
35 	(0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET)
36 
37 #define UTMI_CALIB_CTRL_REG			0x8
38 #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET	8
39 #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK		\
40 	(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
41 #define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET	13
42 #define UTMI_CALIB_CTRL_IMPCAL_START_MASK	\
43 	(0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET)
44 #define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET	22
45 #define UTMI_CALIB_CTRL_PLLCAL_START_MASK	\
46 	(0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET)
47 #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET	23
48 #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK	\
49 	(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
50 #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET	31
51 #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK	\
52 	(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
53 
54 #define UTMI_TX_CH_CTRL_REG			0x0
55 #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET	12
56 #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK		\
57 	(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
58 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET	16
59 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK		\
60 	(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
61 #define UTMI_TX_CH_CTRL_AMP_OFFSET		20
62 #define UTMI_TX_CH_CTRL_AMP_MASK		\
63 	(0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
64 
65 #define UTMI_RX_CH_CTRL0_REG			0x8
66 #define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET	8
67 #define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK	\
68 	(0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET)
69 #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET		15
70 #define UTMI_RX_CH_CTRL0_SQ_DET_MASK		\
71 	(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
72 #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET	28
73 #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK	\
74 	(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
75 
76 #define UTMI_RX_CH_CTRL1_REG			0xc
77 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET	0
78 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK	\
79 	(0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
80 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET	3
81 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK	\
82 	(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
83 
84 #define UTMI_CTRL_STATUS0_REG			0x18
85 #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET	22
86 #define UTMI_CTRL_STATUS0_SUSPENDM_MASK		\
87 	(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
88 #define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET	25
89 #define UTMI_CTRL_STATUS0_TEST_SEL_MASK		\
90 	(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
91 
92 #define UTMI_CHGDTC_CTRL_REG			0x2c
93 #define UTMI_CHGDTC_CTRL_VDAT_OFFSET		8
94 #define UTMI_CHGDTC_CTRL_VDAT_MASK		\
95 	(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
96 #define UTMI_CHGDTC_CTRL_VSRC_OFFSET		10
97 #define UTMI_CHGDTC_CTRL_VSRC_MASK		\
98 	(0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
99 
100 #endif /* _UTMI_PHY_H_ */
101