1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas R-Car Gen3 USB PHY driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 #include <clk.h>
9 #include <div64.h>
10 #include <dm.h>
11 #include <dm/device_compat.h>
12 #include <fdtdec.h>
13 #include <generic-phy.h>
14 #include <malloc.h>
15 #include <reset.h>
16 #include <syscon.h>
17 #include <usb.h>
18 #include <asm/io.h>
19 #include <linux/bitops.h>
20 #include <linux/printk.h>
21 #include <power/regulator.h>
22
23 /* USB2.0 Host registers (original offset is +0x200) */
24 #define USB2_INT_ENABLE 0x000
25 #define USB2_USBCTR 0x00c
26 #define USB2_SPD_RSM_TIMSET 0x10c
27 #define USB2_OC_TIMSET 0x110
28 #define USB2_COMMCTRL 0x600
29 #define USB2_OBINTSTA 0x604
30 #define USB2_OBINTEN 0x608
31 #define USB2_VBCTRL 0x60c
32 #define USB2_LINECTRL1 0x610
33 #define USB2_ADPCTRL 0x630
34
35 /* INT_ENABLE */
36 #define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
37 #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
38 #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
39
40 /* USBCTR */
41 #define USB2_USBCTR_PLL_RST BIT(1)
42
43 /* SPD_RSM_TIMSET */
44 #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
45
46 /* OC_TIMSET */
47 #define USB2_OC_TIMSET_INIT 0x000209ab
48
49 /* COMMCTRL */
50 #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
51
52 /* OBINTSTA and OBINTEN */
53 #define USB2_OBINT_SESSVLDCHG BIT(12)
54 #define USB2_OBINT_IDDIGCHG BIT(11)
55
56 /* VBCTRL */
57 #define USB2_VBCTRL_DRVVBUSSEL BIT(8)
58 #define USB2_VBCTRL_VBOUT BIT(0)
59
60 /* LINECTRL1 */
61 #define USB2_LINECTRL1_DPRPD_EN BIT(19)
62 #define USB2_LINECTRL1_DP_RPD BIT(18)
63 #define USB2_LINECTRL1_DMRPD_EN BIT(17)
64 #define USB2_LINECTRL1_DM_RPD BIT(16)
65
66 /* ADPCTRL */
67 #define USB2_ADPCTRL_OTGSESSVLD BIT(20)
68 #define USB2_ADPCTRL_IDDIG BIT(19)
69 #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
70 #define USB2_ADPCTRL_DRVVBUS BIT(4)
71
72 /* RZ/G2L specific */
73 #define USB2_OBINT_IDCHG_EN BIT(0)
74 #define USB2_LINECTRL1_USB2_IDMON BIT(0)
75
76 /* Device flags */
77 #define RCAR_GEN3_PHY_NO_ADPCTRL BIT(0)
78
79 struct rcar_gen3_phy {
80 fdt_addr_t regs;
81 struct clk clk;
82 struct udevice *vbus_supply;
83 };
84
rcar_gen3_phy_phy_init(struct phy * phy)85 static int rcar_gen3_phy_phy_init(struct phy *phy)
86 {
87 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
88
89 /* Initialize USB2 part */
90 writel(0, priv->regs + USB2_INT_ENABLE);
91 writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
92 writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);
93
94 return 0;
95 }
96
rcar_gen3_phy_phy_exit(struct phy * phy)97 static int rcar_gen3_phy_phy_exit(struct phy *phy)
98 {
99 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
100
101 writel(0, priv->regs + USB2_INT_ENABLE);
102
103 return 0;
104 }
105
rcar_gen3_phy_phy_power_on(struct phy * phy)106 static int rcar_gen3_phy_phy_power_on(struct phy *phy)
107 {
108 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
109 int ret;
110
111 if (priv->vbus_supply) {
112 ret = regulator_set_enable(priv->vbus_supply, true);
113 if (ret)
114 return ret;
115 }
116
117 setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
118 clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
119
120 return 0;
121 }
122
rcar_gen3_phy_phy_power_off(struct phy * phy)123 static int rcar_gen3_phy_phy_power_off(struct phy *phy)
124 {
125 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
126
127 if (!priv->vbus_supply)
128 return 0;
129
130 return regulator_set_enable(priv->vbus_supply, false);
131 }
132
rcar_gen3_phy_check_id(struct phy * phy)133 static bool rcar_gen3_phy_check_id(struct phy *phy)
134 {
135 const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
136 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
137 ulong flags = dev_get_driver_data(phy->dev);
138 u32 val;
139
140 if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
141 val = readl(priv->regs + USB2_LINECTRL1);
142 return !!(val & USB2_LINECTRL1_USB2_IDMON);
143 }
144
145 val = readl(priv->regs + USB2_ADPCTRL);
146 return (val & adpdevmask) == adpdevmask;
147 }
148
rcar_gen3_phy_set_vbus(struct phy * phy,bool enable)149 static void rcar_gen3_phy_set_vbus(struct phy *phy, bool enable)
150 {
151 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
152 ulong flags = dev_get_driver_data(phy->dev);
153 u32 bits = USB2_ADPCTRL_DRVVBUS;
154 u64 reg = USB2_ADPCTRL;
155
156 if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
157 bits = USB2_VBCTRL_VBOUT;
158 reg = USB2_VBCTRL;
159 }
160
161 if (enable)
162 setbits_le32(priv->regs + reg, bits);
163 else
164 clrbits_le32(priv->regs + reg, bits);
165 }
166
rcar_gen3_phy_phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)167 static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
168 int submode)
169 {
170 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
171 ulong flags = dev_get_driver_data(phy->dev);
172
173 if (mode == PHY_MODE_USB_OTG) {
174 if (submode) {
175 u32 obint_enable_bits;
176
177 /* OTG submode is used as initialization indicator */
178 writel(USB2_INT_ENABLE_UCOM_INTEN |
179 USB2_INT_ENABLE_USBH_INTB_EN |
180 USB2_INT_ENABLE_USBH_INTA_EN,
181 priv->regs + USB2_INT_ENABLE);
182 setbits_le32(priv->regs + USB2_VBCTRL,
183 USB2_VBCTRL_DRVVBUSSEL);
184 if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
185 obint_enable_bits = USB2_OBINT_IDCHG_EN;
186 } else {
187 obint_enable_bits = USB2_OBINT_SESSVLDCHG |
188 USB2_OBINT_IDDIGCHG;
189 setbits_le32(priv->regs + USB2_ADPCTRL,
190 USB2_ADPCTRL_IDPULLUP);
191 }
192 writel(obint_enable_bits, priv->regs + USB2_OBINTSTA);
193 setbits_le32(priv->regs + USB2_OBINTEN, obint_enable_bits);
194 clrsetbits_le32(priv->regs + USB2_LINECTRL1,
195 USB2_LINECTRL1_DP_RPD |
196 USB2_LINECTRL1_DM_RPD |
197 USB2_LINECTRL1_DPRPD_EN |
198 USB2_LINECTRL1_DMRPD_EN,
199 USB2_LINECTRL1_DPRPD_EN |
200 USB2_LINECTRL1_DMRPD_EN);
201 }
202
203 if (rcar_gen3_phy_check_id(phy))
204 mode = PHY_MODE_USB_DEVICE;
205 else
206 mode = PHY_MODE_USB_HOST;
207 }
208
209 if (mode == PHY_MODE_USB_HOST) {
210 clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
211 setbits_le32(priv->regs + USB2_LINECTRL1,
212 USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
213 rcar_gen3_phy_set_vbus(phy, true);
214 } else if (mode == PHY_MODE_USB_DEVICE) {
215 setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
216 clrsetbits_le32(priv->regs + USB2_LINECTRL1,
217 USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD,
218 USB2_LINECTRL1_DM_RPD);
219 rcar_gen3_phy_set_vbus(phy, false);
220 } else {
221 dev_err(phy->dev, "Unknown mode %d\n", mode);
222 return -EINVAL;
223 }
224
225 return 0;
226 }
227
228 static const struct phy_ops rcar_gen3_phy_phy_ops = {
229 .init = rcar_gen3_phy_phy_init,
230 .exit = rcar_gen3_phy_phy_exit,
231 .power_on = rcar_gen3_phy_phy_power_on,
232 .power_off = rcar_gen3_phy_phy_power_off,
233 .set_mode = rcar_gen3_phy_phy_set_mode,
234 };
235
rcar_gen3_phy_probe(struct udevice * dev)236 static int rcar_gen3_phy_probe(struct udevice *dev)
237 {
238 struct rcar_gen3_phy *priv = dev_get_priv(dev);
239 int ret;
240
241 priv->regs = dev_read_addr(dev);
242 if (priv->regs == FDT_ADDR_T_NONE)
243 return -EINVAL;
244
245 ret = device_get_supply_regulator(dev, "vbus-supply",
246 &priv->vbus_supply);
247 if (ret && ret != -ENOENT) {
248 pr_err("Failed to get PHY regulator\n");
249 return ret;
250 }
251
252 /* Enable clock */
253 ret = clk_get_by_index(dev, 0, &priv->clk);
254 if (ret)
255 return ret;
256
257 ret = clk_enable(&priv->clk);
258 if (ret)
259 return ret;
260
261 return 0;
262 }
263
rcar_gen3_phy_remove(struct udevice * dev)264 static int rcar_gen3_phy_remove(struct udevice *dev)
265 {
266 struct rcar_gen3_phy *priv = dev_get_priv(dev);
267
268 clk_disable(&priv->clk);
269
270 return 0;
271 }
272
273 static const struct udevice_id rcar_gen3_phy_of_match[] = {
274 {
275 .compatible = "renesas,rcar-gen3-usb2-phy",
276 },
277 {
278 .compatible = "renesas,rzg2l-usb2-phy",
279 .data = RCAR_GEN3_PHY_NO_ADPCTRL,
280 },
281 { },
282 };
283
284 U_BOOT_DRIVER(rcar_gen3_phy) = {
285 .name = "rcar-gen3-phy",
286 .id = UCLASS_PHY,
287 .of_match = rcar_gen3_phy_of_match,
288 .ops = &rcar_gen3_phy_phy_ops,
289 .probe = rcar_gen3_phy_probe,
290 .remove = rcar_gen3_phy_remove,
291 .priv_auto = sizeof(struct rcar_gen3_phy),
292 };
293