1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017 Intel Corp.
4 * Copyright 2019 Google LLC
5 *
6 * Taken partly from coreboot gpio.c
7 */
8
9 #define LOG_CATEGORY UCLASS_GPIO
10
11 #include <dm.h>
12 #include <dt-structs.h>
13 #include <log.h>
14 #include <p2sb.h>
15 #include <asm/intel_pinctrl.h>
16 #include <asm-generic/gpio.h>
17 #include <asm/intel_pinctrl_defs.h>
18
19 static const struct reset_mapping rst_map[] = {
20 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
21 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
22 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
23 };
24
25 /* Groups for each community */
26 static const struct pad_group apl_community_n_groups[] = {
27 INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */
28 INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */
29 INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */
30 };
31
32 static const struct pad_group apl_community_w_groups[] = {
33 INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1), /* WEST 0 */
34 INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
35 };
36
37 static const struct pad_group apl_community_sw_groups[] = {
38 INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */
39 INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */
40 };
41
42 static const struct pad_group apl_community_nw_groups[] = {
43 INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */
44 INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106), /* NORTHWEST 1 */
45 INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */
46 };
47
48 /* TODO(sjg@chromium.org): Consider moving this to device tree */
49 static const struct pad_community apl_gpio_communities[] = {
50 {
51 .port = PID_GPIO_N,
52 .first_pad = N_OFFSET,
53 .last_pad = SVID0_CLK,
54 .num_gpi_regs = NUM_N_GPI_REGS,
55 .gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
56 + NUM_SW_GPI_REGS,
57 .pad_cfg_base = PAD_CFG_BASE,
58 .host_own_reg_0 = HOSTSW_OWN_REG_0,
59 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
60 .gpi_int_en_reg_0 = GPI_INT_EN_0,
61 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
62 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
63 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
64 .name = "GPIO_GPE_N",
65 .reset_map = rst_map,
66 .num_reset_vals = ARRAY_SIZE(rst_map),
67 .groups = apl_community_n_groups,
68 .num_groups = ARRAY_SIZE(apl_community_n_groups),
69 }, {
70 .port = PID_GPIO_NW,
71 .first_pad = NW_OFFSET,
72 .last_pad = GPIO_123,
73 .num_gpi_regs = NUM_NW_GPI_REGS,
74 .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
75 .pad_cfg_base = PAD_CFG_BASE,
76 .host_own_reg_0 = HOSTSW_OWN_REG_0,
77 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
78 .gpi_int_en_reg_0 = GPI_INT_EN_0,
79 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
80 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
81 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
82 .name = "GPIO_GPE_NW",
83 .reset_map = rst_map,
84 .num_reset_vals = ARRAY_SIZE(rst_map),
85 .groups = apl_community_nw_groups,
86 .num_groups = ARRAY_SIZE(apl_community_nw_groups),
87 }, {
88 .port = PID_GPIO_W,
89 .first_pad = W_OFFSET,
90 .last_pad = SUSPWRDNACK,
91 .num_gpi_regs = NUM_W_GPI_REGS,
92 .gpi_status_offset = NUM_SW_GPI_REGS,
93 .pad_cfg_base = PAD_CFG_BASE,
94 .host_own_reg_0 = HOSTSW_OWN_REG_0,
95 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
96 .gpi_int_en_reg_0 = GPI_INT_EN_0,
97 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
98 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
99 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
100 .name = "GPIO_GPE_W",
101 .reset_map = rst_map,
102 .num_reset_vals = ARRAY_SIZE(rst_map),
103 .groups = apl_community_w_groups,
104 .num_groups = ARRAY_SIZE(apl_community_w_groups),
105 }, {
106 .port = PID_GPIO_SW,
107 .first_pad = SW_OFFSET,
108 .last_pad = LPC_FRAMEB,
109 .num_gpi_regs = NUM_SW_GPI_REGS,
110 .gpi_status_offset = 0,
111 .pad_cfg_base = PAD_CFG_BASE,
112 .host_own_reg_0 = HOSTSW_OWN_REG_0,
113 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
114 .gpi_int_en_reg_0 = GPI_INT_EN_0,
115 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
116 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
117 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
118 .name = "GPIO_GPE_SW",
119 .reset_map = rst_map,
120 .num_reset_vals = ARRAY_SIZE(rst_map),
121 .groups = apl_community_sw_groups,
122 .num_groups = ARRAY_SIZE(apl_community_sw_groups),
123 },
124 };
125
apl_pinctrl_of_to_plat(struct udevice * dev)126 static int apl_pinctrl_of_to_plat(struct udevice *dev)
127 {
128 struct p2sb_child_plat *pplat;
129 const struct pad_community *comm = NULL;
130 int i;
131
132 #if CONFIG_IS_ENABLED(OF_PLATDATA)
133 struct apl_gpio_plat *plat = dev_get_plat(dev);
134 int ret;
135
136 /*
137 * It would be nice to do this in the bind() method, but with
138 * of-platdata binding happens in the order that DM finds things in the
139 * linker list (i.e. alphabetical order by driver name). So the GPIO
140 * device may well be bound before its parent (p2sb), and this call
141 * will fail if p2sb is not bound yet.
142 */
143 ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id);
144 if (ret)
145 return log_msg_ret("Could not set port id", ret);
146 #endif
147 /* Attach this device to its community structure */
148 pplat = dev_get_parent_plat(dev);
149 for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
150 if (apl_gpio_communities[i].port == pplat->pid)
151 comm = &apl_gpio_communities[i];
152 }
153
154 return intel_pinctrl_of_to_plat(dev, comm, 2);
155 }
156
157 #if CONFIG_IS_ENABLED(OF_REAL)
158 static const struct udevice_id apl_gpio_ids[] = {
159 { .compatible = "intel,apl-pinctrl"},
160 { }
161 };
162 #endif
163
164 U_BOOT_DRIVER(intel_apl_pinctrl) = {
165 .name = "intel_apl_pinctrl",
166 .id = UCLASS_PINCTRL,
167 .of_match = of_match_ptr(apl_gpio_ids),
168 .probe = intel_pinctrl_probe,
169 .ops = &intel_pinctrl_ops,
170 #if CONFIG_IS_ENABLED(OF_REAL)
171 .bind = dm_scan_fdt_dev,
172 #endif
173 .of_to_plat = apl_pinctrl_of_to_plat,
174 .priv_auto = sizeof(struct intel_pinctrl_priv),
175 .plat_auto = sizeof(struct apl_gpio_plat),
176 };
177