1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 *
5 * Dave Liu <daveliu@freescale.com>
6 * based on source code of Shlomi Gridish
7 */
8
9 #include <linux/errno.h>
10 #include <asm/io.h>
11 #include <asm/immap_83xx.h>
12
13 #if defined(CONFIG_PINCTRL)
14 #include <dm.h>
15 #include <dm/device_compat.h>
16 #include <dm/pinctrl.h>
17 #include <linux/ioport.h>
18
19 /**
20 * struct qe_io_plat
21 *
22 * @base: Base register address
23 * @num_par_io_ports number of io ports
24 */
25 struct qe_io_plat {
26 qepio83xx_t *base;
27 u32 num_io_ports;
28 };
29 #endif
30
31 #define NUM_OF_PINS 32
32
33 /** qe_cfg_iopin configure one io pin setting
34 *
35 * @par_io: pointer to parallel I/O base
36 * @port: io pin port
37 * @pin: io pin number which get configured
38 * @dir: direction of io pin 2 bits valid
39 * 00 = pin disabled
40 * 01 = output
41 * 10 = input
42 * 11 = pin is I/O
43 * @open_drain: is pin open drain
44 * @assign: pin assignment registers select the function of the pin
45 */
qe_cfg_iopin(qepio83xx_t * par_io,u8 port,u8 pin,int dir,int open_drain,int assign)46 static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
47 int open_drain, int assign)
48 {
49 u32 dbit_mask;
50 u32 dbit_dir;
51 u32 dbit_asgn;
52 u32 bit_mask;
53 u32 tmp_val;
54 int offset;
55
56 offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
57
58 /* Calculate pin location and 2bit mask and dir */
59 dbit_mask = (u32)(0x3 << offset);
60 dbit_dir = (u32)(dir << offset);
61
62 /* Setup the direction */
63 tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
64 in_be32(&par_io->ioport[port].dir2) :
65 in_be32(&par_io->ioport[port].dir1);
66
67 if (pin > (NUM_OF_PINS / 2) - 1) {
68 out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
69 out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
70 } else {
71 out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
72 out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
73 }
74
75 /* Calculate pin location for 1bit mask */
76 bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
77
78 /* Setup the open drain */
79 tmp_val = in_be32(&par_io->ioport[port].podr);
80 if (open_drain)
81 out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
82 else
83 out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
84
85 /* Setup the assignment */
86 tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
87 in_be32(&par_io->ioport[port].ppar2) :
88 in_be32(&par_io->ioport[port].ppar1);
89 dbit_asgn = (u32)(assign << offset);
90
91 /* Clear and set 2 bits mask */
92 if (pin > (NUM_OF_PINS / 2) - 1) {
93 out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
94 out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
95 } else {
96 out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
97 out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
98 }
99 }
100
101 #if !defined(CONFIG_PINCTRL)
102 /** qe_config_iopin configure one io pin setting
103 *
104 * @port: io pin port
105 * @pin: io pin number which get configured
106 * @dir: direction of io pin 2 bits valid
107 * 00 = pin disabled
108 * 01 = output
109 * 10 = input
110 * 11 = pin is I/O
111 * @open_drain: is pin open drain
112 * @assign: pin assignment registers select the function of the pin
113 */
qe_config_iopin(u8 port,u8 pin,int dir,int open_drain,int assign)114 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
115 {
116 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
117 qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
118
119 qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
120 }
121 #else
qe_io_of_to_plat(struct udevice * dev)122 static int qe_io_of_to_plat(struct udevice *dev)
123 {
124 struct qe_io_plat *plat = dev_get_plat(dev);
125 fdt_addr_t addr;
126
127 addr = dev_read_addr(dev);
128 if (addr == FDT_ADDR_T_NONE)
129 return -EINVAL;
130
131 plat->base = (qepio83xx_t *)addr;
132 if (dev_read_u32(dev, "num-ports", &plat->num_io_ports))
133 return -EINVAL;
134
135 return 0;
136 }
137
138 /**
139 * par_io_of_config_node config
140 * @dev: pointer to pinctrl device
141 * @pio: ofnode of pinconfig property
142 */
par_io_of_config_node(struct udevice * dev,ofnode pio)143 static int par_io_of_config_node(struct udevice *dev, ofnode pio)
144 {
145 struct qe_io_plat *plat = dev_get_plat(dev);
146 qepio83xx_t *par_io = plat->base;
147 const unsigned int *pio_map;
148 int pio_map_len;
149
150 pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len);
151 if (!pio_map)
152 return -ENOENT;
153
154 pio_map_len /= sizeof(unsigned int);
155 if ((pio_map_len % 6) != 0) {
156 dev_err(dev, "%s: pio-map format wrong!\n", __func__);
157 return -EINVAL;
158 }
159
160 while (pio_map_len > 0) {
161 /*
162 * column pio_map[5] from linux (has_irq) not
163 * supported in u-boot yet.
164 */
165 qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1],
166 (int)pio_map[2], (int)pio_map[3],
167 (int)pio_map[4]);
168 pio_map += 6;
169 pio_map_len -= 6;
170 }
171 return 0;
172 }
173
par_io_of_config(struct udevice * dev)174 int par_io_of_config(struct udevice *dev)
175 {
176 u32 phandle;
177 ofnode pio;
178 int err;
179
180 err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle);
181 if (err) {
182 dev_err(dev, "%s: pio-handle not available\n", __func__);
183 return err;
184 }
185
186 pio = ofnode_get_by_phandle(phandle);
187 if (!ofnode_valid(pio)) {
188 dev_err(dev, "%s: unable to find node\n", __func__);
189 return -EINVAL;
190 }
191
192 /* To Do: find pinctrl device and pass it */
193 return par_io_of_config_node(NULL, pio);
194 }
195
196 /*
197 * This is not nice!
198 * pinsettings should work with "pinctrl-" properties.
199 * Unfortunately on mpc83xx powerpc linux device trees
200 * devices handle this with "pio-handle" properties ...
201 *
202 * Even worser, old board code inits all par_io
203 * pins in one step, if U-Boot uses the device
204 * or not. So init all par_io definitions here too
205 * as linux does this also.
206 */
config_qe_ioports(struct udevice * dev)207 static void config_qe_ioports(struct udevice *dev)
208 {
209 ofnode ofn;
210
211 for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn);
212 ofn = dev_read_next_subnode(ofn)) {
213 /*
214 * ignore errors here, as may the subnode
215 * has no pio-handle
216 */
217 par_io_of_config_node(dev, ofn);
218 }
219 }
220
par_io_pinctrl_probe(struct udevice * dev)221 static int par_io_pinctrl_probe(struct udevice *dev)
222 {
223 config_qe_ioports(dev);
224
225 return 0;
226 }
227
par_io_pinctrl_set_state(struct udevice * dev,struct udevice * config)228 static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config)
229 {
230 return 0;
231 }
232
233 const struct pinctrl_ops par_io_pinctrl_ops = {
234 .set_state = par_io_pinctrl_set_state,
235 };
236
237 static const struct udevice_id par_io_pinctrl_match[] = {
238 { .compatible = "fsl,mpc8360-par_io"},
239 { /* sentinel */ }
240 };
241
242 U_BOOT_DRIVER(par_io_pinctrl) = {
243 .name = "par-io-pinctrl",
244 .id = UCLASS_PINCTRL,
245 .of_match = of_match_ptr(par_io_pinctrl_match),
246 .probe = par_io_pinctrl_probe,
247 .of_to_plat = qe_io_of_to_plat,
248 .plat_auto = sizeof(struct qe_io_plat),
249 .ops = &par_io_pinctrl_ops,
250 #if CONFIG_IS_ENABLED(OF_REAL)
251 .flags = DM_FLAG_PRE_RELOC,
252 #endif
253 };
254 #endif
255