1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Pinctrl driver for STMicroelectronics STi SoCs
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
7 */
8
9 #include <bitfield.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <dm/pinctrl.h>
17 #include <linux/bug.h>
18 #include <linux/libfdt.h>
19 #include <linux/printk.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define MAX_STI_PINCONF_ENTRIES 7
24 /* Output enable */
25 #define OE (1 << 27)
26 /* Pull Up */
27 #define PU (1 << 26)
28 /* Open Drain */
29 #define OD (1 << 25)
30
31 /* User-frendly defines for Pin Direction */
32 /* oe = 0, pu = 0, od = 0 */
33 #define IN (0)
34 /* oe = 0, pu = 1, od = 0 */
35 #define IN_PU (PU)
36 /* oe = 1, pu = 0, od = 0 */
37 #define OUT (OE)
38 /* oe = 1, pu = 1, od = 0 */
39 #define OUT_PU (OE | PU)
40 /* oe = 1, pu = 0, od = 1 */
41 #define BIDIR (OE | OD)
42 /* oe = 1, pu = 1, od = 1 */
43 #define BIDIR_PU (OE | PU | OD)
44
45 struct sti_pinctrl_plat {
46 struct regmap *regmap;
47 };
48
49 struct sti_pin_desc {
50 unsigned char bank;
51 unsigned char pin;
52 unsigned char alt;
53 int dir;
54 };
55
56 /*
57 * PIO alternative Function selector
58 */
sti_alternate_select(struct udevice * dev,struct sti_pin_desc * pin_desc)59 void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
60 {
61 struct sti_pinctrl_plat *plat = dev_get_plat(dev);
62 unsigned long sysconf, *sysconfreg;
63 int alt = pin_desc->alt;
64 int bank = pin_desc->bank;
65 int pin = pin_desc->pin;
66
67 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start;
68
69 switch (bank) {
70 case 0 ... 5: /* in "SBC Bank" */
71 sysconfreg += bank;
72 break;
73 case 10 ... 20: /* in "FRONT Bank" */
74 sysconfreg += bank - 10;
75 break;
76 case 30 ... 35: /* in "REAR Bank" */
77 sysconfreg += bank - 30;
78 break;
79 case 40 ... 42: /* in "FLASH Bank" */
80 sysconfreg += bank - 40;
81 break;
82 default:
83 BUG();
84 return;
85 }
86
87 sysconf = readl(sysconfreg);
88 sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
89 writel(sysconf, sysconfreg);
90 }
91
92 /* pin configuration */
sti_pin_configure(struct udevice * dev,struct sti_pin_desc * pin_desc)93 void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
94 {
95 struct sti_pinctrl_plat *plat = dev_get_plat(dev);
96 int bit;
97 int oe = 0, pu = 0, od = 0;
98 unsigned long *sysconfreg;
99 int bank = pin_desc->bank;
100
101 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start + 40;
102
103 /*
104 * NOTE: The PIO configuration for the PIO pins in the
105 * "FLASH Bank" are different from all the other banks!
106 * Specifically, the output-enable pin control register
107 * (SYS_CFG_3040) and the pull-up pin control register
108 * (SYS_CFG_3050), are both classed as being "reserved".
109 * Hence, we do not write to these registers to configure
110 * the OE and PU features for PIOs in this bank. However,
111 * the open-drain pin control register (SYS_CFG_3060)
112 * follows the style of the other banks, and so we can
113 * treat that register normally.
114 *
115 * Being pedantic, we should configure the PU and PD features
116 * in the "FLASH Bank" explicitly instead using the four
117 * SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
118 * would necessitate passing in the alternate function number
119 * to this function, and adding some horrible complexity here.
120 * Alternatively, we could just perform 4 32-bit "pokes" to
121 * these four SYS_CFG registers early in the initialization.
122 * In practice, these four SYS_CFG registers are correct
123 * after a reset, and U-Boot does not need to change them, so
124 * we (cheat and) rely on these registers being correct.
125 * WARNING: Please be aware of this (pragmatic) behaviour!
126 */
127 int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
128
129 switch (pin_desc->dir) {
130 case IN:
131 oe = 0; pu = 0; od = 0;
132 break;
133 case IN_PU:
134 oe = 0; pu = 1; od = 0;
135 break;
136 case OUT:
137 oe = 1; pu = 0; od = 0;
138 break;
139 case BIDIR:
140 oe = 1; pu = 0; od = 1;
141 break;
142 case BIDIR_PU:
143 oe = 1; pu = 1; od = 1;
144 break;
145
146 default:
147 pr_err("%s invalid direction value: 0x%x\n",
148 __func__, pin_desc->dir);
149 BUG();
150 break;
151 }
152
153 switch (bank) {
154 case 0 ... 5: /* in "SBC Bank" */
155 sysconfreg += bank / 4;
156 break;
157 case 10 ... 20: /* in "FRONT Bank" */
158 bank -= 10;
159 sysconfreg += bank / 4;
160 break;
161 case 30 ... 35: /* in "REAR Bank" */
162 bank -= 30;
163 sysconfreg += bank / 4;
164 break;
165 case 40 ... 42: /* in "FLASH Bank" */
166 bank -= 40;
167 sysconfreg += bank / 4;
168 flashss = 1; /* pin is in the Flash Sub-System */
169 break;
170 default:
171 BUG();
172 return;
173 }
174
175 bit = ((bank * 8) + pin_desc->pin) % 32;
176
177 /*
178 * set the "Output Enable" pin control
179 * but, do nothing if in the flashSS
180 */
181 if (!flashss) {
182 if (oe)
183 generic_set_bit(bit, sysconfreg);
184 else
185 generic_clear_bit(bit, sysconfreg);
186 }
187
188 sysconfreg += 10; /* skip to next set of syscfg registers */
189
190 /*
191 * set the "Pull Up" pin control
192 * but, do nothing if in the FlashSS
193 */
194
195 if (!flashss) {
196 if (pu)
197 generic_set_bit(bit, sysconfreg);
198 else
199 generic_clear_bit(bit, sysconfreg);
200 }
201
202 sysconfreg += 10; /* skip to next set of syscfg registers */
203
204 /* set the "Open Drain Enable" pin control */
205 if (od)
206 generic_set_bit(bit, sysconfreg);
207 else
208 generic_clear_bit(bit, sysconfreg);
209 }
210
sti_pinctrl_set_state(struct udevice * dev,struct udevice * config)211 static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
212 {
213 struct fdtdec_phandle_args args;
214 const void *blob = gd->fdt_blob;
215 const char *prop_name;
216 int node = dev_of_offset(config);
217 int property_offset, prop_len;
218 int pinconf_node, ret, count;
219 const char *bank_name;
220 u32 cells[MAX_STI_PINCONF_ENTRIES];
221
222 struct sti_pin_desc pin_desc;
223
224 /* go to next node "st,pins" which contains the pins configuration */
225 pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
226
227 /*
228 * parse each pins configuration which looks like :
229 * pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
230 */
231
232 fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
233 fdt_getprop_by_offset(blob, property_offset, &prop_name,
234 &prop_len);
235
236 /* extract the bank of the pin description */
237 ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
238 prop_name, "#gpio-cells",
239 0, 0, &args);
240 if (ret < 0) {
241 pr_err("Can't get the gpio bank phandle: %d\n", ret);
242 return ret;
243 }
244
245 bank_name = fdt_getprop(blob, args.node, "st,bank-name",
246 &count);
247 if (count < 0) {
248 pr_err("Can't find bank-name property %d\n", count);
249 return -EINVAL;
250 }
251
252 pin_desc.bank = trailing_strtoln(bank_name, NULL);
253
254 count = fdtdec_get_int_array_count(blob, pinconf_node,
255 prop_name, cells,
256 ARRAY_SIZE(cells));
257 if (count < 0) {
258 pr_err("Bad pin configuration array %d\n", count);
259 return -EINVAL;
260 }
261
262 if (count > MAX_STI_PINCONF_ENTRIES) {
263 pr_err("Unsupported pinconf array count %d\n", count);
264 return -EINVAL;
265 }
266
267 pin_desc.pin = cells[1];
268 pin_desc.alt = cells[2];
269 pin_desc.dir = cells[3];
270
271 sti_alternate_select(dev, &pin_desc);
272 sti_pin_configure(dev, &pin_desc);
273 };
274
275 return 0;
276 }
277
sti_pinctrl_probe(struct udevice * dev)278 static int sti_pinctrl_probe(struct udevice *dev)
279 {
280 struct sti_pinctrl_plat *plat = dev_get_plat(dev);
281 struct udevice *syscon;
282 int err;
283
284 /* get corresponding syscon phandle */
285 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
286 "st,syscfg", &syscon);
287 if (err) {
288 pr_err("unable to find syscon device\n");
289 return err;
290 }
291
292 plat->regmap = syscon_get_regmap(syscon);
293 if (!plat->regmap) {
294 pr_err("unable to find regmap\n");
295 return -ENODEV;
296 }
297
298 return 0;
299 }
300
301 static const struct udevice_id sti_pinctrl_ids[] = {
302 { .compatible = "st,stih407-sbc-pinctrl" },
303 { .compatible = "st,stih407-front-pinctrl" },
304 { .compatible = "st,stih407-rear-pinctrl" },
305 { .compatible = "st,stih407-flash-pinctrl" },
306 { }
307 };
308
309 const struct pinctrl_ops sti_pinctrl_ops = {
310 .set_state = sti_pinctrl_set_state,
311 };
312
313 U_BOOT_DRIVER(pinctrl_sti) = {
314 .name = "pinctrl_sti",
315 .id = UCLASS_PINCTRL,
316 .of_match = sti_pinctrl_ids,
317 .ops = &sti_pinctrl_ops,
318 .probe = sti_pinctrl_probe,
319 .plat_auto = sizeof(struct sti_pinctrl_plat),
320 .ops = &sti_pinctrl_ops,
321 };
322