1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Pinctrl driver for Microchip PIC32 SoCs
4 * Copyright (c) 2015 Microchip Technology Inc.
5 * Written by Purna Chandra Mandal <purna.mandal@microchip.com>
6 */
7 #include <dm.h>
8 #include <errno.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <dm/pinctrl.h>
13 #include <linux/bitops.h>
14 #include <mach/pic32.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 /* PIC32 has 10 peripheral ports with 16 pins each.
19 * Ports are marked PORTA-PORTK or PORT0-PORT9.
20 */
21 enum {
22 PIC32_PORT_A = 0,
23 PIC32_PORT_B = 1,
24 PIC32_PORT_C = 2,
25 PIC32_PORT_D = 3,
26 PIC32_PORT_E = 4,
27 PIC32_PORT_F = 5,
28 PIC32_PORT_G = 6,
29 PIC32_PORT_H = 7,
30 PIC32_PORT_J = 8, /* no PORT_I */
31 PIC32_PORT_K = 9,
32 PIC32_PINS_PER_PORT = 16,
33 };
34
35 #define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
36 #define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
37
38 /* pin configuration descriptor */
39 struct pic32_pin_config {
40 u16 port; /* port number */
41 u16 pin; /* pin number in the port */
42 u32 config; /* one of PIN_CONFIG_* */
43 };
44 #define PIN_CONFIG(_prt, _pin, _cfg) \
45 {.port = (_prt), .pin = (_pin), .config = (_cfg), }
46
47 /* In PIC32 muxing is performed at pin-level through two
48 * different set of registers - one set for input functions,
49 * and other for output functions.
50 * Pin configuration is handled through port register.
51 */
52 /* Port control registers */
53 struct pic32_reg_port {
54 struct pic32_reg_atomic ansel;
55 struct pic32_reg_atomic tris;
56 struct pic32_reg_atomic port;
57 struct pic32_reg_atomic lat;
58 struct pic32_reg_atomic odc;
59 struct pic32_reg_atomic cnpu;
60 struct pic32_reg_atomic cnpd;
61 struct pic32_reg_atomic cncon;
62 struct pic32_reg_atomic unused[8];
63 };
64
65 /* Input function mux registers */
66 struct pic32_reg_in_mux {
67 u32 unused0;
68 u32 int1[4];
69 u32 unused1;
70 u32 t2ck[8];
71 u32 ic1[9];
72 u32 unused2;
73 u32 ocfar;
74 u32 unused3;
75 u32 u1rx;
76 u32 u1cts;
77 u32 u2rx;
78 u32 u2cts;
79 u32 u3rx;
80 u32 u3cts;
81 u32 u4rx;
82 u32 u4cts;
83 u32 u5rx;
84 u32 u5cts;
85 u32 u6rx;
86 u32 u6cts;
87 u32 unused4;
88 u32 sdi1;
89 u32 ss1;
90 u32 unused5;
91 u32 sdi2;
92 u32 ss2;
93 u32 unused6;
94 u32 sdi3;
95 u32 ss3;
96 u32 unused7;
97 u32 sdi4;
98 u32 ss4;
99 u32 unused8;
100 u32 sdi5;
101 u32 ss5;
102 u32 unused9;
103 u32 sdi6;
104 u32 ss6;
105 u32 c1rx;
106 u32 c2rx;
107 u32 refclki1;
108 u32 refclki2;
109 u32 refclki3;
110 u32 refclki4;
111 };
112
113 /* output mux register offset */
114 #define PPS_OUT(__port, __pin) \
115 (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
116
117 struct pic32_pinctrl_priv {
118 struct pic32_reg_in_mux *mux_in; /* mux input function */
119 struct pic32_reg_port *pinconf; /* pin configuration*/
120 void __iomem *mux_out; /* mux output function */
121 };
122
123 enum {
124 PERIPH_ID_UART1,
125 PERIPH_ID_UART2,
126 PERIPH_ID_ETH,
127 PERIPH_ID_USB,
128 PERIPH_ID_SDHCI,
129 PERIPH_ID_I2C1,
130 PERIPH_ID_I2C2,
131 PERIPH_ID_SPI1,
132 PERIPH_ID_SPI2,
133 PERIPH_ID_SQI,
134 };
135
pic32_pinconfig_one(struct pic32_pinctrl_priv * priv,u32 port_nr,u32 pin,u32 param)136 static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv,
137 u32 port_nr, u32 pin, u32 param)
138 {
139 struct pic32_reg_port *port;
140
141 port = &priv->pinconf[port_nr];
142 switch (param) {
143 case PIN_CONFIG_PIC32_DIGITAL:
144 writel(BIT(pin), &port->ansel.clr);
145 break;
146 case PIN_CONFIG_PIC32_ANALOG:
147 writel(BIT(pin), &port->ansel.set);
148 break;
149 case PIN_CONFIG_INPUT_ENABLE:
150 writel(BIT(pin), &port->tris.set);
151 break;
152 case PIN_CONFIG_OUTPUT:
153 writel(BIT(pin), &port->tris.clr);
154 break;
155 case PIN_CONFIG_BIAS_PULL_UP:
156 writel(BIT(pin), &port->cnpu.set);
157 break;
158 case PIN_CONFIG_BIAS_PULL_DOWN:
159 writel(BIT(pin), &port->cnpd.set);
160 break;
161 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
162 writel(BIT(pin), &port->odc.set);
163 break;
164 default:
165 break;
166 }
167
168 return 0;
169 }
170
pic32_pinconfig_set(struct pic32_pinctrl_priv * priv,const struct pic32_pin_config * list,int count)171 static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv,
172 const struct pic32_pin_config *list, int count)
173 {
174 int i;
175
176 for (i = 0 ; i < count; i++)
177 pic32_pinconfig_one(priv, list[i].port,
178 list[i].pin, list[i].config);
179
180 return 0;
181 }
182
pic32_eth_pin_config(struct udevice * dev)183 static void pic32_eth_pin_config(struct udevice *dev)
184 {
185 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
186 const struct pic32_pin_config configs[] = {
187 /* EMDC - D11 */
188 PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_PIC32_DIGITAL),
189 PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT),
190 /* ETXEN */
191 PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_PIC32_DIGITAL),
192 PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT),
193 /* ECRSDV */
194 PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_PIC32_DIGITAL),
195 PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_INPUT_ENABLE),
196 /* ERXD0 */
197 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_PIC32_DIGITAL),
198 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_INPUT_ENABLE),
199 PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_BIAS_PULL_DOWN),
200 /* ERXD1 */
201 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_PIC32_DIGITAL),
202 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_INPUT_ENABLE),
203 PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_BIAS_PULL_DOWN),
204 /* EREFCLK */
205 PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_PIC32_DIGITAL),
206 PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_INPUT_ENABLE),
207 /* ETXD1 */
208 PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_PIC32_DIGITAL),
209 PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT),
210 /* ETXD0 */
211 PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_PIC32_DIGITAL),
212 PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT),
213 /* EMDIO */
214 PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_PIC32_DIGITAL),
215 PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_INPUT_ENABLE),
216 /* ERXERR */
217 PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_PIC32_DIGITAL),
218 PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_INPUT_ENABLE),
219 };
220
221 pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
222 }
223
pic32_sdhci_pin_config(struct udevice * dev)224 static void pic32_sdhci_pin_config(struct udevice *dev)
225 {
226 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
227 const struct pic32_pin_config configs[] = {
228 /* SDWP - H2 */
229 PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL),
230 /* SDCD - A0 */
231 PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL),
232 /* SDCMD - D4 */
233 PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL),
234 /* SDCK - A6 */
235 PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL),
236 /* SDDATA0 - G13 */
237 PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL),
238 /* SDDATA1 - G12 */
239 PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL),
240 /* SDDATA2 - G14 */
241 PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL),
242 /* SDDATA3 - A7 */
243 PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL),
244 };
245
246 pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
247 }
248
pic32_pinctrl_request(struct udevice * dev,int func,int flags)249 static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
250 {
251 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
252
253 switch (func) {
254 case PERIPH_ID_UART2:
255 /* PPS for U2 RX/TX */
256 writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G, 9));
257 writel(0x05, &priv->mux_in->u2rx); /* B0 */
258 /* set digital mode */
259 pic32_pinconfig_one(priv, PIC32_PORT_G, 9,
260 PIN_CONFIG_PIC32_DIGITAL);
261 pic32_pinconfig_one(priv, PIC32_PORT_B, 0,
262 PIN_CONFIG_PIC32_DIGITAL);
263 break;
264 case PERIPH_ID_ETH:
265 pic32_eth_pin_config(dev);
266 break;
267 case PERIPH_ID_SDHCI:
268 pic32_sdhci_pin_config(dev);
269 break;
270 default:
271 debug("%s: unknown-unhandled case\n", __func__);
272 break;
273 }
274
275 return 0;
276 }
277
pic32_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)278 static int pic32_pinctrl_get_periph_id(struct udevice *dev,
279 struct udevice *periph)
280 {
281 int ret;
282 u32 cell[2];
283
284 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
285 "interrupts", cell, ARRAY_SIZE(cell));
286 if (ret < 0)
287 return -EINVAL;
288
289 /* interrupt number */
290 switch (cell[0]) {
291 case 112 ... 114:
292 return PERIPH_ID_UART1;
293 case 145 ... 147:
294 return PERIPH_ID_UART2;
295 case 109 ... 111:
296 return PERIPH_ID_SPI1;
297 case 142 ... 144:
298 return PERIPH_ID_SPI2;
299 case 115 ... 117:
300 return PERIPH_ID_I2C1;
301 case 148 ... 150:
302 return PERIPH_ID_I2C2;
303 case 132 ... 133:
304 return PERIPH_ID_USB;
305 case 169:
306 return PERIPH_ID_SQI;
307 case 191:
308 return PERIPH_ID_SDHCI;
309 case 153:
310 return PERIPH_ID_ETH;
311 default:
312 break;
313 }
314
315 return -ENOENT;
316 }
317
pic32_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)318 static int pic32_pinctrl_set_state_simple(struct udevice *dev,
319 struct udevice *periph)
320 {
321 int func;
322
323 debug("%s: periph %s\n", __func__, periph->name);
324 func = pic32_pinctrl_get_periph_id(dev, periph);
325 if (func < 0)
326 return func;
327 return pic32_pinctrl_request(dev, func, 0);
328 }
329
330 static struct pinctrl_ops pic32_pinctrl_ops = {
331 .set_state_simple = pic32_pinctrl_set_state_simple,
332 .request = pic32_pinctrl_request,
333 .get_periph_id = pic32_pinctrl_get_periph_id,
334 };
335
pic32_pinctrl_probe(struct udevice * dev)336 static int pic32_pinctrl_probe(struct udevice *dev)
337 {
338 struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
339 struct fdt_resource res;
340 void *fdt = (void *)gd->fdt_blob;
341 int node = dev_of_offset(dev);
342 int ret;
343
344 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
345 "ppsin", &res);
346 if (ret < 0) {
347 printf("pinctrl: resource \"ppsin\" not found\n");
348 return ret;
349 }
350 priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
351
352 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
353 "ppsout", &res);
354 if (ret < 0) {
355 printf("pinctrl: resource \"ppsout\" not found\n");
356 return ret;
357 }
358 priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
359
360 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
361 "port", &res);
362 if (ret < 0) {
363 printf("pinctrl: resource \"port\" not found\n");
364 return ret;
365 }
366 priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
367
368 return 0;
369 }
370
371 static const struct udevice_id pic32_pinctrl_ids[] = {
372 { .compatible = "microchip,pic32mzda-pinctrl" },
373 { }
374 };
375
376 U_BOOT_DRIVER(pinctrl_pic32) = {
377 .name = "pinctrl_pic32",
378 .id = UCLASS_PINCTRL,
379 .of_match = pic32_pinctrl_ids,
380 .ops = &pic32_pinctrl_ops,
381 .probe = pic32_pinctrl_probe,
382 .bind = dm_scan_fdt_dev,
383 .priv_auto = sizeof(struct pic32_pinctrl_priv),
384 };
385