1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * TLMM driver for Qualcomm APQ8016, APQ8096
4 *
5 * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
6 *
7 */
8
9 #include <dm.h>
10 #include <errno.h>
11 #include <asm/io.h>
12 #include <dm/device_compat.h>
13 #include <dm/device-internal.h>
14 #include <dm/lists.h>
15 #include <asm/gpio.h>
16 #include <dm/pinctrl.h>
17 #include <linux/bitops.h>
18 #include <linux/bitmap.h>
19 #include <linux/bug.h>
20 #include <mach/gpio.h>
21
22 #include "pinctrl-qcom.h"
23
24 #define MSM_PINCTRL_MAX_PINS 256
25
26 struct msm_pinctrl_priv {
27 phys_addr_t base;
28 struct msm_pinctrl_data *data;
29 DECLARE_BITMAP(reserved_map, MSM_PINCTRL_MAX_PINS);
30 };
31
32 #define GPIO_CONFIG_REG(priv, x) \
33 (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
34
35 #define GPIO_IN_OUT_REG(priv, x) \
36 (GPIO_CONFIG_REG(priv, x) + 0x4)
37
38 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
39 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
40 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
41 #define TLMM_GPIO_OUTPUT_MASK BIT(1)
42 #define TLMM_GPIO_OE_MASK BIT(9)
43
44 /* GPIO register shifts. */
45 #define GPIO_OUT_SHIFT 1
46
47 static const struct pinconf_param msm_conf_params[] = {
48 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
49 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
50 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
51 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_UP, 1 },
52 { "output-high", PIN_CONFIG_OUTPUT, 1, },
53 { "output-low", PIN_CONFIG_OUTPUT, 0, },
54 };
55
msm_get_functions_count(struct udevice * dev)56 static int msm_get_functions_count(struct udevice *dev)
57 {
58 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
59
60 return priv->data->functions_count;
61 }
62
msm_get_pins_count(struct udevice * dev)63 static int msm_get_pins_count(struct udevice *dev)
64 {
65 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
66
67 return priv->data->pin_data.pin_count;
68 }
69
msm_get_function_name(struct udevice * dev,unsigned int selector)70 static const char *msm_get_function_name(struct udevice *dev,
71 unsigned int selector)
72 {
73 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
74
75 return priv->data->get_function_name(dev, selector);
76 }
77
msm_pinctrl_parse_ranges(struct udevice * dev)78 static int msm_pinctrl_parse_ranges(struct udevice *dev)
79 {
80 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
81 ofnode node = dev_ofnode(dev);
82 int ret, count, i;
83 u32 *ranges;
84
85 if (ofnode_read_prop(node, "gpio-reserved-ranges", &count)) {
86 if (count % 2 == 1) {
87 dev_err(dev, "gpio-reserved-ranges must be a multiple of 2\n");
88 return -EINVAL;
89 }
90
91 ranges = malloc(count);
92 if (!ranges)
93 return -ENOMEM;
94
95 ret = ofnode_read_u32_array(node, "gpio-reserved-ranges", ranges, count / 4);
96 if (ret) {
97 dev_err(dev, "failed to read gpio-reserved-ranges array (%d)\n", ret);
98 return ret;
99 }
100
101 for (i = 0; i < count / 4; i += 2) {
102 if (ranges[i] >= MSM_PINCTRL_MAX_PINS ||
103 (ranges[i] + ranges[i + 1]) >= MSM_PINCTRL_MAX_PINS) {
104 dev_err(dev, "invalid reserved-range (%d;%d)\n",
105 ranges[i], ranges[i + 1]);
106 return -EINVAL;
107 }
108
109 bitmap_set(priv->reserved_map, ranges[i], ranges[i + 1]);
110 }
111
112 free(ranges);
113 }
114
115 return 0;
116 }
117
msm_pinctrl_probe(struct udevice * dev)118 static int msm_pinctrl_probe(struct udevice *dev)
119 {
120 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
121 int ret;
122
123 priv->base = dev_read_addr(dev);
124 priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
125
126 ret = msm_pinctrl_parse_ranges(dev);
127 if (ret) {
128 printf("Couldn't parse reserved GPIO ranges!\n");
129 return ret;
130 }
131
132 return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
133 }
134
msm_get_pin_name(struct udevice * dev,unsigned int selector)135 static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
136 {
137 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
138
139 return priv->data->get_pin_name(dev, selector);
140 }
141
msm_pinmux_set(struct udevice * dev,unsigned int pin_selector,unsigned int func_selector)142 static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
143 unsigned int func_selector)
144 {
145 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
146 int func = priv->data->get_function_mux(pin_selector, func_selector);
147
148 if (func < 0)
149 return func;
150
151 if (msm_pinctrl_is_reserved(dev, pin_selector))
152 return -EPERM;
153
154 /* Always NOP for special pins, assume they're in the correct state */
155 if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
156 return 0;
157
158 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
159 TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2);
160 return 0;
161 }
162
msm_pinconf_set_special(struct msm_pinctrl_priv * priv,unsigned int pin_selector,unsigned int param,unsigned int argument)163 static int msm_pinconf_set_special(struct msm_pinctrl_priv *priv, unsigned int pin_selector,
164 unsigned int param, unsigned int argument)
165 {
166 unsigned int offset = pin_selector - priv->data->pin_data.special_pins_start;
167 const struct msm_special_pin_data *data;
168
169 if (!priv->data->pin_data.special_pins_data)
170 return 0;
171
172 data = &priv->data->pin_data.special_pins_data[offset];
173
174 switch (param) {
175 case PIN_CONFIG_DRIVE_STRENGTH:
176 argument = (argument / 2) - 1;
177 clrsetbits_le32(priv->base + data->ctl_reg,
178 GENMASK(2, 0) << data->drv_bit,
179 argument << data->drv_bit);
180 break;
181 case PIN_CONFIG_BIAS_DISABLE:
182 clrbits_le32(priv->base + data->ctl_reg,
183 TLMM_GPIO_PULL_MASK << data->pull_bit);
184 break;
185 case PIN_CONFIG_BIAS_PULL_UP:
186 clrsetbits_le32(priv->base + data->ctl_reg,
187 TLMM_GPIO_PULL_MASK << data->pull_bit,
188 argument << data->pull_bit);
189 break;
190 default:
191 return 0;
192 }
193
194 return 0;
195 }
196
msm_pinconf_set(struct udevice * dev,unsigned int pin_selector,unsigned int param,unsigned int argument)197 static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
198 unsigned int param, unsigned int argument)
199 {
200 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
201
202 if (msm_pinctrl_is_reserved(dev, pin_selector))
203 return -EPERM;
204
205 if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
206 return msm_pinconf_set_special(priv, pin_selector, param, argument);
207
208 switch (param) {
209 case PIN_CONFIG_DRIVE_STRENGTH:
210 argument = (argument / 2) - 1;
211 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
212 TLMM_DRV_STRENGTH_MASK, argument << 6);
213 break;
214 case PIN_CONFIG_BIAS_DISABLE:
215 clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
216 TLMM_GPIO_PULL_MASK);
217 break;
218 case PIN_CONFIG_BIAS_PULL_UP:
219 clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
220 TLMM_GPIO_PULL_MASK, argument);
221 break;
222 case PIN_CONFIG_OUTPUT:
223 writel(argument << GPIO_OUT_SHIFT,
224 priv->base + GPIO_IN_OUT_REG(priv, pin_selector));
225 setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
226 TLMM_GPIO_OE_MASK);
227 break;
228 default:
229 return 0;
230 }
231
232 return 0;
233 }
234
235 struct pinctrl_ops msm_pinctrl_ops = {
236 .get_pins_count = msm_get_pins_count,
237 .get_pin_name = msm_get_pin_name,
238 .set_state = pinctrl_generic_set_state,
239 .pinmux_set = msm_pinmux_set,
240 .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
241 .pinconf_params = msm_conf_params,
242 .pinconf_set = msm_pinconf_set,
243 .get_functions_count = msm_get_functions_count,
244 .get_function_name = msm_get_function_name,
245 };
246
msm_pinctrl_bind(struct udevice * dev)247 int msm_pinctrl_bind(struct udevice *dev)
248 {
249 ofnode node = dev_ofnode(dev);
250 struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
251 struct driver *drv;
252 struct udevice *pinctrl_dev;
253 const char *name;
254 int ret;
255
256 if (!data->pin_data.special_pins_start)
257 dev_warn(dev, "Special pins start index not defined!\n");
258
259 drv = lists_driver_lookup_name("pinctrl_qcom");
260 if (!drv)
261 return -ENOENT;
262
263 ret = device_bind_with_driver_data(dev_get_parent(dev), drv, ofnode_get_name(node), (ulong)data,
264 dev_ofnode(dev), &pinctrl_dev);
265 if (ret)
266 return ret;
267
268 ofnode_get_property(node, "gpio-controller", &ret);
269 if (ret < 0)
270 return 0;
271
272 /* Get the name of gpio node */
273 name = ofnode_get_name(node);
274 if (!name)
275 return -EINVAL;
276
277 drv = lists_driver_lookup_name("gpio_msm");
278 if (!drv) {
279 printf("Can't find gpio_msm driver\n");
280 return -ENODEV;
281 }
282
283 /* Bind gpio device as a child of the pinctrl device */
284 ret = device_bind_with_driver_data(pinctrl_dev, drv,
285 name, (ulong)&data->pin_data, node, NULL);
286 if (ret) {
287 device_unbind(pinctrl_dev);
288 return ret;
289 }
290
291 return 0;
292 }
293
294 U_BOOT_DRIVER(pinctrl_qcom) = {
295 .name = "pinctrl_qcom",
296 .id = UCLASS_PINCTRL,
297 .priv_auto = sizeof(struct msm_pinctrl_priv),
298 .ops = &msm_pinctrl_ops,
299 .probe = msm_pinctrl_probe,
300 };
301
msm_pinctrl_is_reserved(struct udevice * dev,unsigned int pin)302 bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin)
303 {
304 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
305
306 if (pin >= MSM_PINCTRL_MAX_PINS)
307 return false;
308
309 return test_bit(pin, priv->reserved_map);
310 }
311