1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Texas Instruments' AM654 DDRSS driver
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9 #include <clk.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <ram.h>
13 #include <asm/io.h>
14 #include <power-domain.h>
15 #include <dm/device_compat.h>
16 #include <power/regulator.h>
17 #include "k3-am654-ddrss.h"
18
19 void sdelay(unsigned long loops);
20 u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
21 u32 bound);
22
23 #define LDELAY 10000
24
25 /* DDRSS PHY configuration register fixed values */
26 #define DDRSS_DDRPHY_RANKIDR_RANK0 0
27
28 /**
29 * struct am654_ddrss_desc - Description of ddrss integration.
30 * @dev: DDRSS device pointer
31 * @ddrss_ss_cfg: DDRSS wrapper logic region base address
32 * @ddrss_ctl_cfg: DDRSS controller region base address
33 * @ddrss_phy_cfg: DDRSS PHY region base address
34 * @ddrss_clk: DDRSS clock description
35 * @vtt_supply: VTT Supply regulator
36 * @ddrss_pwrdmn: DDRSS power domain description
37 * @params: SDRAM configuration parameters
38 */
39 struct am654_ddrss_desc {
40 struct udevice *dev;
41 void __iomem *ddrss_ss_cfg;
42 void __iomem *ddrss_ctl_cfg;
43 void __iomem *ddrss_phy_cfg;
44 struct clk ddrss_clk;
45 struct udevice *vtt_supply;
46 struct power_domain ddrcfg_pwrdmn;
47 struct power_domain ddrdata_pwrdmn;
48 struct ddrss_params params;
49 };
50
ddrss_readl(void __iomem * addr,unsigned int offset)51 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
52 {
53 return readl(addr + offset);
54 }
55
ddrss_writel(void __iomem * addr,unsigned int offset,u32 data)56 static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
57 u32 data)
58 {
59 debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
60 writel(data, addr + offset);
61 }
62
63 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
64 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
65
am654_ddrss_get_type(struct am654_ddrss_desc * ddrss)66 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
67 {
68 return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
69 }
70
71 /**
72 * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
73 *
74 * After detecting the DDR type this function will pause until the
75 * initialization is complete. Each DDR type has mask of multiple bits.
76 * The size of the field depends on the DDR Type. If the initialization
77 * does not complete and error will be returned and will cause the boot to halt.
78 *
79 */
am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc * ddrss)80 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
81 {
82 u32 val, mask;
83
84 val = am654_ddrss_get_type(ddrss);
85
86 switch (val) {
87 case DDR_TYPE_LPDDR4:
88 case DDR_TYPE_DDR4:
89 mask = DDR4_STAT_MODE_MASK;
90 break;
91 case DDR_TYPE_DDR3:
92 mask = DDR3_STAT_MODE_MASK;
93 break;
94 default:
95 printf("Unsupported DDR type 0x%x\n", val);
96 return -EINVAL;
97 }
98
99 if (!wait_on_value(mask, DDR_MODE_NORMAL,
100 ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
101 return -ETIMEDOUT;
102
103 return 0;
104 }
105
106 /**
107 * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
108 * @dev: corresponding ddrss device
109 */
am654_ddrss_ctrl_configuration(struct am654_ddrss_desc * ddrss)110 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
111 {
112 struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
113 struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
114 struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
115 struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
116 struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
117 u32 val;
118
119 debug("%s: DDR controller register configuration started\n", __func__);
120
121 ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
122 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
123 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
124
125 ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
126 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
127 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
128 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
129
130 ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
131 ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
132 ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
133 ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
134 ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
135 ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
136 ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
137
138 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
139 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
140 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
141 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
142 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
143 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
144 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
145 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
146 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
147 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
148 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
149 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
150 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
151 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
152
153 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
154 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
155
156 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
157 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
158 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
159 ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
160
161 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
162 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
163 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
164 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
165 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
166 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
167 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
168 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
169 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
170 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
171 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
172 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
173
174 ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
175 ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
176
177 /* Disable refreshes */
178 val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
179 val |= 0x01;
180 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
181
182 debug("%s: DDR controller configuration completed\n", __func__);
183 }
184
185 #define ddrss_phy_writel(off, val) \
186 do { \
187 ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \
188 sdelay(10); /* Delay at least 20 clock cycles */ \
189 } while (0)
190
191 #define ddrss_phy_readl(off) \
192 ({ \
193 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \
194 sdelay(10); /* Delay at least 20 clock cycles */ \
195 val; \
196 })
197
198 /**
199 * am654_ddrss_phy_configuration() - Configure PHY specific registers
200 * @ddrss: corresponding ddrss device
201 */
am654_ddrss_phy_configuration(struct am654_ddrss_desc * ddrss)202 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
203 {
204 struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
205 struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
206 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
207 struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
208 struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
209
210 debug("%s: DDR phy register configuration started\n", __func__);
211
212 ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
213 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
214 ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
215 ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
216 ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
217
218 ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
219 ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
220 ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
221 ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
222 ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
223
224 ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
225
226 ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
227 ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
228
229 ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
230
231 ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
232 ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
233 ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
234 ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
235 ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
236 ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
237 ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
238
239 ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
240 ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
241 ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
242
243 ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
244 ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
245 ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
246 ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
247 ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
248 ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
249 ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
250 ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
251 ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
252 ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
253 ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
254 ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
255
256 ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
257
258 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
259 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
260 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
261
262 ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
263 ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
264
265 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
266 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
267 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
268 ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
269
270 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, cfg->ddrphy_dx2gcr0);
271 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR1, cfg->ddrphy_dx2gcr1);
272 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR2, cfg->ddrphy_dx2gcr2);
273 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR3, cfg->ddrphy_dx2gcr3);
274
275 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, cfg->ddrphy_dx3gcr0);
276 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR1, cfg->ddrphy_dx3gcr1);
277 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR2, cfg->ddrphy_dx3gcr2);
278 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR3, cfg->ddrphy_dx3gcr3);
279
280 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
281 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
282 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
283 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
284
285 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
286 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
287 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
288 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
289
290 ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
291 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
292 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
293 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
294 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
295
296 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
297
298 ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
299 ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
300 ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
301 ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
302 ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
303
304 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
305 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
306 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
307
308 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
309 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
310 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
311
312 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
313 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
314 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
315
316 debug("%s: DDR phy register configuration completed\n", __func__);
317 }
318
__phy_builtin_init_routine(struct am654_ddrss_desc * ddrss,u32 init_value,u32 sts_mask,u32 err_mask)319 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
320 u32 init_value, u32 sts_mask,
321 u32 err_mask)
322 {
323 int ret;
324
325 ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
326
327 sdelay(5); /* Delay at least 10 clock cycles */
328
329 if (!wait_on_value(sts_mask, sts_mask,
330 ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
331 return -ETIMEDOUT;
332
333 sdelay(16); /* Delay at least 32 clock cycles */
334
335 ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
336 debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
337 if (ret & err_mask)
338 return -EINVAL;
339
340 return 0;
341 }
342
write_leveling(struct am654_ddrss_desc * ddrss)343 int write_leveling(struct am654_ddrss_desc *ddrss)
344 {
345 int ret;
346
347 debug("%s: Write leveling started\n", __func__);
348
349 ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
350 PGSR0_WLERR_MASK);
351 if (ret) {
352 if (ret == -ETIMEDOUT)
353 printf("%s: ERROR: Write leveling timedout\n",
354 __func__);
355 else
356 printf("%s:ERROR: Write leveling failed\n", __func__);
357 return ret;
358 }
359
360 debug("%s: Write leveling completed\n", __func__);
361 return 0;
362 }
363
read_dqs_training(struct am654_ddrss_desc * ddrss)364 int read_dqs_training(struct am654_ddrss_desc *ddrss)
365 {
366 int ret;
367
368 debug("%s: Read DQS training started\n", __func__);
369
370 ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
371 PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
372 if (ret) {
373 if (ret == -ETIMEDOUT)
374 printf("%s: ERROR: Read DQS timedout\n", __func__);
375 else
376 printf("%s:ERROR: Read DQS Gate training failed\n",
377 __func__);
378 return ret;
379 }
380
381 debug("%s: Read DQS training completed\n", __func__);
382 return 0;
383 }
384
dqs2dq_training(struct am654_ddrss_desc * ddrss)385 int dqs2dq_training(struct am654_ddrss_desc *ddrss)
386 {
387 int ret;
388
389 debug("%s: DQS2DQ training started\n", __func__);
390
391 ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
392 PGSR0_DQS2DQDONE_MASK,
393 PGSR0_DQS2DQERR_MASK);
394 if (ret) {
395 if (ret == -ETIMEDOUT)
396 printf("%s: ERROR: DQS2DQ training timedout\n",
397 __func__);
398 else
399 printf("%s:ERROR: DQS2DQ training failed\n",
400 __func__);
401 return ret;
402 }
403
404 debug("%s: DQS2DQ training completed\n", __func__);
405 return 0;
406 }
407
write_leveling_adjustment(struct am654_ddrss_desc * ddrss)408 int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
409 {
410 int ret;
411
412 debug("%s: Write Leveling adjustment\n", __func__);
413 ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
414 PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
415 if (ret) {
416 if (ret == -ETIMEDOUT)
417 printf("%s:ERROR: Write Leveling adjustment timedout\n",
418 __func__);
419 else
420 printf("%s: ERROR: Write Leveling adjustment failed\n",
421 __func__);
422 return ret;
423 }
424 return 0;
425 }
426
rest_training(struct am654_ddrss_desc * ddrss)427 int rest_training(struct am654_ddrss_desc *ddrss)
428 {
429 int ret;
430
431 debug("%s: Rest of the training started\n", __func__);
432
433 debug("%s: Read Deskew adjustment\n", __func__);
434 ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
435 PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
436 if (ret) {
437 if (ret == -ETIMEDOUT)
438 printf("%s: ERROR: Read Deskew timedout\n", __func__);
439 else
440 printf("%s: ERROR: Read Deskew failed\n", __func__);
441 return ret;
442 }
443
444 debug("%s: Write Deskew adjustment\n", __func__);
445 ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
446 PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
447 if (ret) {
448 if (ret == -ETIMEDOUT)
449 printf("%s: ERROR: Write Deskew timedout\n", __func__);
450 else
451 printf("%s: ERROR: Write Deskew failed\n", __func__);
452 return ret;
453 }
454
455 debug("%s: Read Eye training\n", __func__);
456 ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
457 PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
458 if (ret) {
459 if (ret == -ETIMEDOUT)
460 printf("%s: ERROR: Read Eye training timedout\n",
461 __func__);
462 else
463 printf("%s: ERROR: Read Eye training failed\n",
464 __func__);
465 return ret;
466 }
467
468 debug("%s: Write Eye training\n", __func__);
469 ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
470 PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
471 if (ret) {
472 if (ret == -ETIMEDOUT)
473 printf("%s: ERROR: Write Eye training timedout\n",
474 __func__);
475 else
476 printf("%s: ERROR: Write Eye training failed\n",
477 __func__);
478 return ret;
479 }
480 return 0;
481 }
482
VREF_training(struct am654_ddrss_desc * ddrss)483 int VREF_training(struct am654_ddrss_desc *ddrss)
484 {
485 int ret;
486 debug("%s: VREF training\n", __func__);
487 ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
488 PGSR0_VERR_MASK);
489 if (ret) {
490 if (ret == -ETIMEDOUT)
491 printf("%s: ERROR: VREF training timedout\n", __func__);
492 else
493 printf("%s: ERROR: VREF training failed\n", __func__);
494 return ret;
495 }
496 return 0;
497 }
498
enable_dqs_pd(struct am654_ddrss_desc * ddrss)499 int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
500 {
501 u32 val;
502
503 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
504 val &= ~0xFF;
505 val |= 0xF7;
506 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
507
508 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
509 val &= ~0xFF;
510 val |= 0xF7;
511 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
512
513 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
514 val &= ~0xFF;
515 val |= 0xF7;
516 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
517
518 sdelay(16);
519 return 0;
520 }
521
disable_dqs_pd(struct am654_ddrss_desc * ddrss)522 int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
523 {
524 u32 val;
525
526 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
527 val &= ~0xFF;
528 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
529
530 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
531 val &= ~0xFF;
532 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
533
534 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
535 val &= ~0xFF;
536 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
537
538 sdelay(16);
539 return 0;
540 }
541
cleanup_training(struct am654_ddrss_desc * ddrss)542 int cleanup_training(struct am654_ddrss_desc *ddrss)
543 {
544 u32 val;
545 u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
546
547 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
548 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
549 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
550 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
551 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
552
553 rddly = dgsl0;
554 if (dgsl1 < rddly)
555 rddly = dgsl1;
556 if (dgsl2 < rddly)
557 rddly = dgsl2;
558 if (dgsl3 < rddly)
559 rddly = dgsl3;
560
561 rddly += 5;
562
563 /* Update rddly based on dgsl values */
564 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
565 val |= (rddly << 20);
566 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
567
568 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
569 val |= (rddly << 20);
570 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
571
572 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
573 val |= (rddly << 20);
574 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
575
576 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
577 val |= (rddly << 20);
578 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
579
580 /*
581 * Add system latency derived from training back into rd2wr and wr2rd
582 * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
583 * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
584 */
585
586 /* Select rank 0 */
587 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
588
589 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
590 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
591 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
592 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
593
594 /* Find maximum value across all bytes */
595 rd2wr_wr2rd = dgsl0;
596 if (dgsl1 > rd2wr_wr2rd)
597 rd2wr_wr2rd = dgsl1;
598 if (dgsl2 > rd2wr_wr2rd)
599 rd2wr_wr2rd = dgsl2;
600 if (dgsl3 > rd2wr_wr2rd)
601 rd2wr_wr2rd = dgsl3;
602
603 rd2wr_wr2rd >>= 1;
604
605 /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
606 /* Clear VSWCTL.sw_done */
607 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
608 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
609 /* Adjust rd2wr */
610 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
611 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
612 (rd2wr_wr2rd << 8));
613 /* Adjust wr2rd */
614 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
615 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
616 rd2wr_wr2rd);
617 /* Set VSWCTL.sw_done */
618 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
619 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
620 /* Wait until settings are applied */
621 while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
622 /* Do nothing */
623 };
624
625 debug("%s: Rest of the training completed\n", __func__);
626 return 0;
627 }
628
629 /**
630 * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
631 * device attached to ddrss.
632 * @dev: corresponding ddrss device
633 *
634 * Does all the initialization sequence that is required to get attached
635 * ddr in a working state. After this point, ddr should be accessible.
636 * Return: 0 if all went ok, else corresponding error message.
637 */
am654_ddrss_init(struct am654_ddrss_desc * ddrss)638 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
639 {
640 int ret;
641 u32 val;
642 struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
643
644 debug("Starting DDR initialization...\n");
645
646 debug("%s(ddrss=%p)\n", __func__, ddrss);
647
648 ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
649 reg->ddrss_v2h_ctl_reg);
650
651 am654_ddrss_ctrl_configuration(ddrss);
652
653 /* Release the reset to the controller */
654 clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
655 SS_CTL_REG_CTL_ARST_MASK);
656
657 am654_ddrss_phy_configuration(ddrss);
658
659 debug("Starting DDR training...\n");
660 ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
661 if (ret) {
662 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
663 return ret;
664 }
665
666 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
667 PGSR0_DRAM_INIT_MASK, 0);
668 if (ret) {
669 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
670 return ret;
671 }
672
673 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
674 if (ret) {
675 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
676 __func__);
677 return ret;
678 }
679
680 val = am654_ddrss_get_type(ddrss);
681
682 switch (val) {
683 case DDR_TYPE_LPDDR4:
684
685 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
686 PGSR0_DRAM_INIT_MASK, 0);
687 if (ret) {
688 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
689 ret);
690 return ret;
691 }
692
693 /* must perform DRAM_INIT twice for LPDDR4 */
694 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
695 PGSR0_DRAM_INIT_MASK, 0);
696 if (ret) {
697 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
698 ret);
699 return ret;
700 }
701
702 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
703 if (ret) {
704 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
705 __func__);
706 return ret;
707 }
708
709 ret = write_leveling(ddrss);
710 if (ret)
711 return ret;
712
713 ret = enable_dqs_pd(ddrss);
714 if (ret)
715 return ret;
716
717 ret = read_dqs_training(ddrss);
718 if (ret)
719 return ret;
720
721 ret = disable_dqs_pd(ddrss);
722 if (ret)
723 return ret;
724
725 ret = dqs2dq_training(ddrss);
726 if (ret)
727 return ret;
728
729 ret = write_leveling_adjustment(ddrss);
730 if (ret)
731 return ret;
732
733 ret = rest_training(ddrss);
734 if (ret)
735 return ret;
736
737 ret = VREF_training(ddrss);
738 if (ret)
739 return ret;
740
741 debug("LPDDR4 training complete\n");
742 break;
743
744 case DDR_TYPE_DDR4:
745
746 debug("Starting DDR4 training\n");
747
748 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
749 PGSR0_DRAM_INIT_MASK, 0);
750 if (ret) {
751 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
752 ret);
753 return ret;
754 }
755
756 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
757 if (ret) {
758 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
759 __func__);
760 return ret;
761 }
762
763 ret = write_leveling(ddrss);
764 if (ret)
765 return ret;
766
767 ret = read_dqs_training(ddrss);
768 if (ret)
769 return ret;
770
771 ret = write_leveling_adjustment(ddrss);
772 if (ret)
773 return ret;
774
775 ret = rest_training(ddrss);
776 if (ret)
777 return ret;
778
779 ret = VREF_training(ddrss);
780 if (ret)
781 return ret;
782 debug("DDR4 training complete\n");
783 break;
784
785 case DDR_TYPE_DDR3:
786
787 debug("Starting DDR3 training\n");
788
789 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
790 PGSR0_DRAM_INIT_MASK, 0);
791 if (ret) {
792 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
793 ret);
794 return ret;
795 }
796
797 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
798 if (ret) {
799 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
800 __func__);
801 return ret;
802 }
803
804 ret = write_leveling(ddrss);
805 if (ret)
806 return ret;
807
808 ret = enable_dqs_pd(ddrss);
809 if (ret)
810 return ret;
811
812 ret = read_dqs_training(ddrss);
813 if (ret)
814 return ret;
815
816 ret = disable_dqs_pd(ddrss);
817 if (ret)
818 return ret;
819
820 ret = write_leveling_adjustment(ddrss);
821 if (ret)
822 return ret;
823
824 ret = rest_training(ddrss);
825 if (ret)
826 return ret;
827
828 debug("DDR3 training complete\n");
829 break;
830 default:
831 printf("%s: ERROR: Unsupported DDR type\n", __func__);
832 return -EINVAL;
833 }
834
835 ret = cleanup_training(ddrss);
836 if (ret)
837 return ret;
838
839 /* Enabling refreshes after training is done */
840 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
841 ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
842
843 /* Disable PUBMODE after training is done */
844 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
845 ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
846
847 debug("Completed DDR training\n");
848
849 return 0;
850 }
851
852 /**
853 * am654_ddrss_power_on() - Enable power and clocks for ddrss
854 * @dev: corresponding ddrss device
855 *
856 * Tries to enable all the corresponding clocks to the ddrss and sets it
857 * to the right frequency and then power on the ddrss.
858 * Return: 0 if all went ok, else corresponding error message.
859 */
am654_ddrss_power_on(struct am654_ddrss_desc * ddrss)860 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
861 {
862 int ret;
863
864 debug("%s(ddrss=%p)\n", __func__, ddrss);
865
866 ret = clk_enable(&ddrss->ddrss_clk);
867 if (ret) {
868 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
869 return ret;
870 }
871
872 ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
873 if (ret) {
874 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
875 return ret;
876 }
877
878 ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
879 if (ret) {
880 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
881 return ret;
882 }
883
884 /* VTT enable */
885 #if CONFIG_IS_ENABLED(DM_REGULATOR)
886 device_get_supply_regulator(ddrss->dev, "vtt-supply",
887 &ddrss->vtt_supply);
888 ret = regulator_set_value(ddrss->vtt_supply, 3300000);
889 if (ret == 0)
890 debug("VTT regulator enabled\n");
891 #endif
892
893 return 0;
894 }
895
896 /**
897 * am654_ddrss_ofdata_to_priv() - generate private data from device tree
898 * @dev: corresponding ddrss device
899 *
900 * Return: 0 if all went ok, else corresponding error message.
901 */
am654_ddrss_ofdata_to_priv(struct udevice * dev)902 static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
903 {
904 struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
905 void *reg;
906 int ret;
907
908 debug("%s(dev=%p)\n", __func__, dev);
909
910 ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
911 if (ret) {
912 dev_err(dev, "clk_get failed: %d\n", ret);
913 return ret;
914 }
915
916 ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
917 if (ret) {
918 dev_err(dev, "power_domain_get() failed: %d\n", ret);
919 return ret;
920 }
921
922 ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
923 if (ret) {
924 dev_err(dev, "power_domain_get() failed: %d\n", ret);
925 return ret;
926 }
927
928 reg = dev_read_addr_name_ptr(dev, "ss");
929 if (!reg) {
930 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
931 return -EINVAL;
932 }
933 ddrss->ddrss_ss_cfg = reg;
934
935 reg = dev_read_addr_name_ptr(dev, "ctl");
936 if (!reg) {
937 dev_err(dev, "No reg property for Controller region\n");
938 return -EINVAL;
939 }
940 ddrss->ddrss_ctl_cfg = reg;
941
942 reg = dev_read_addr_name_ptr(dev, "phy");
943 if (!reg) {
944 dev_err(dev, "No reg property for PHY region\n");
945 return -EINVAL;
946 }
947 ddrss->ddrss_phy_cfg = reg;
948
949 ret = dev_read_u32_array(dev, "ti,ss-reg",
950 (u32 *)&ddrss->params.ss_reg,
951 sizeof(ddrss->params.ss_reg) / sizeof(u32));
952 if (ret) {
953 dev_err(dev, "Cannot read ti,ss-reg params\n");
954 return ret;
955 }
956
957 ret = dev_read_u32_array(dev, "ti,ctl-reg",
958 (u32 *)&ddrss->params.ctl_reg,
959 sizeof(ddrss->params.ctl_reg) / sizeof(u32));
960 if (ret) {
961 dev_err(dev, "Cannot read ti,ctl-reg params\n");
962 return ret;
963 }
964
965 ret = dev_read_u32_array(dev, "ti,ctl-crc",
966 (u32 *)&ddrss->params.ctl_crc,
967 sizeof(ddrss->params.ctl_crc) / sizeof(u32));
968 if (ret) {
969 dev_err(dev, "Cannot read ti,ctl-crc params\n");
970 return ret;
971 }
972
973 ret = dev_read_u32_array(dev, "ti,ctl-ecc",
974 (u32 *)&ddrss->params.ctl_ecc,
975 sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
976 if (ret) {
977 dev_err(dev, "Cannot read ti,ctl-ecc params\n");
978 return ret;
979 }
980
981 ret = dev_read_u32_array(dev, "ti,ctl-map",
982 (u32 *)&ddrss->params.ctl_map,
983 sizeof(ddrss->params.ctl_map) / sizeof(u32));
984 if (ret) {
985 dev_err(dev, "Cannot read ti,ctl-map params\n");
986 return ret;
987 }
988
989 ret = dev_read_u32_array(dev, "ti,ctl-pwr",
990 (u32 *)&ddrss->params.ctl_pwr,
991 sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
992 if (ret) {
993 dev_err(dev, "Cannot read ti,ctl-pwr params\n");
994 return ret;
995 }
996
997 ret = dev_read_u32_array(dev, "ti,ctl-timing",
998 (u32 *)&ddrss->params.ctl_timing,
999 sizeof(ddrss->params.ctl_timing) /
1000 sizeof(u32));
1001 if (ret) {
1002 dev_err(dev, "Cannot read ti,ctl-timing params\n");
1003 return ret;
1004 }
1005
1006 ret = dev_read_u32_array(dev, "ti,phy-cfg",
1007 (u32 *)&ddrss->params.phy_cfg,
1008 sizeof(ddrss->params.phy_cfg) / sizeof(u32));
1009 if (ret) {
1010 dev_err(dev, "Cannot read ti,phy-cfg params\n");
1011 return ret;
1012 }
1013
1014 ret = dev_read_u32_array(dev, "ti,phy-ctl",
1015 (u32 *)&ddrss->params.phy_ctrl,
1016 sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
1017 if (ret) {
1018 dev_err(dev, "Cannot read ti,phy-ctl params\n");
1019 return ret;
1020 }
1021
1022 ret = dev_read_u32_array(dev, "ti,phy-ioctl",
1023 (u32 *)&ddrss->params.phy_ioctl,
1024 sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
1025 if (ret) {
1026 dev_err(dev, "Cannot read ti,phy-ioctl params\n");
1027 return ret;
1028 }
1029
1030 ret = dev_read_u32_array(dev, "ti,phy-timing",
1031 (u32 *)&ddrss->params.phy_timing,
1032 sizeof(ddrss->params.phy_timing) /
1033 sizeof(u32));
1034 if (ret) {
1035 dev_err(dev, "Cannot read ti,phy-timing params\n");
1036 return ret;
1037 }
1038
1039 ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
1040 sizeof(ddrss->params.phy_zq) / sizeof(u32));
1041 if (ret) {
1042 dev_err(dev, "Cannot read ti,phy-zq params\n");
1043 return ret;
1044 }
1045
1046 return ret;
1047 }
1048
1049 /**
1050 * am654_ddrss_probe() - Basic probe
1051 * @dev: corresponding ddrss device
1052 *
1053 * Return: 0 if all went ok, else corresponding error message
1054 */
am654_ddrss_probe(struct udevice * dev)1055 static int am654_ddrss_probe(struct udevice *dev)
1056 {
1057 struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
1058 int ret;
1059
1060 debug("%s(dev=%p)\n", __func__, dev);
1061
1062 ret = am654_ddrss_ofdata_to_priv(dev);
1063 if (ret)
1064 return ret;
1065
1066 ddrss->dev = dev;
1067 ret = am654_ddrss_power_on(ddrss);
1068 if (ret)
1069 return ret;
1070
1071 ret = am654_ddrss_init(ddrss);
1072
1073 return ret;
1074 }
1075
am654_ddrss_get_info(struct udevice * dev,struct ram_info * info)1076 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
1077 {
1078 return 0;
1079 }
1080
1081 static struct ram_ops am654_ddrss_ops = {
1082 .get_info = am654_ddrss_get_info,
1083 };
1084
1085 static const struct udevice_id am654_ddrss_ids[] = {
1086 { .compatible = "ti,am654-ddrss" },
1087 { }
1088 };
1089
1090 U_BOOT_DRIVER(am654_ddrss) = {
1091 .name = "am654_ddrss",
1092 .id = UCLASS_RAM,
1093 .of_match = am654_ddrss_ids,
1094 .ops = &am654_ddrss_ops,
1095 .probe = am654_ddrss_probe,
1096 .priv_auto = sizeof(struct am654_ddrss_desc),
1097 };
1098