1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2001, 2002, 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Keith Outwater, keith_outwater@mvis.com`
6 * Steven Scholz, steven.scholz@imc-berlin.de
7 */
8
9 /*
10 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
11 * DS1307 and DS1338/9 Real Time Clock (RTC).
12 *
13 * based on ds1337.c
14 */
15
16 #include <config.h>
17 #include <command.h>
18 #include <dm.h>
19 #include <log.h>
20 #include <rtc.h>
21 #include <i2c.h>
22
23 enum ds_type {
24 ds_1307,
25 ds_1337,
26 ds_1339,
27 ds_1340,
28 m41t11,
29 mcp794xx,
30 };
31
32 /*
33 * RTC register addresses
34 */
35 #define RTC_SEC_REG_ADDR 0x00
36 #define RTC_MIN_REG_ADDR 0x01
37 #define RTC_HR_REG_ADDR 0x02
38 #define RTC_DAY_REG_ADDR 0x03
39 #define RTC_DATE_REG_ADDR 0x04
40 #define RTC_MON_REG_ADDR 0x05
41 #define RTC_YR_REG_ADDR 0x06
42 #define RTC_CTL_REG_ADDR 0x07
43
44 #define DS1337_CTL_REG_ADDR 0x0e
45 #define DS1337_STAT_REG_ADDR 0x0f
46 #define DS1340_STAT_REG_ADDR 0x09
47
48 #define RTC_STAT_BIT_OSF 0x80
49
50 #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
51
52 /* DS1307-specific bits */
53 #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
54 #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
55 #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
56 #define RTC_CTL_BIT_OUT 0x80 /* Output Control */
57
58 /* DS1337-specific bits */
59 #define DS1337_CTL_BIT_RS1 0x08 /* Rate select 1 */
60 #define DS1337_CTL_BIT_RS2 0x10 /* Rate select 2 */
61 #define DS1337_CTL_BIT_EOSC 0x80 /* Enable Oscillator */
62
63 /* DS1340-specific bits */
64 #define DS1340_SEC_BIT_EOSC 0x80 /* Enable Oscillator */
65 #define DS1340_CTL_BIT_OUT 0x80 /* Output Control */
66
67 /* MCP7941X-specific bits */
68 #define MCP7941X_BIT_ST 0x80
69 #define MCP7941X_BIT_VBATEN 0x08
70
71 #ifndef CONFIG_DM_RTC
72
73 /*---------------------------------------------------------------------*/
74 #undef DEBUG_RTC
75
76 #ifdef DEBUG_RTC
77 #define DEBUGR(fmt, args...) printf(fmt, ##args)
78 #else
79 #define DEBUGR(fmt, args...)
80 #endif
81 /*---------------------------------------------------------------------*/
82
83 #ifndef CFG_SYS_I2C_RTC_ADDR
84 # define CFG_SYS_I2C_RTC_ADDR 0x68
85 #endif
86
87 #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
88 # error The DS1307 is specified only up to 100kHz!
89 #endif
90
91 static uchar rtc_read (uchar reg);
92 static void rtc_write (uchar reg, uchar val);
93
94 /*
95 * Get the current time from the RTC
96 */
rtc_get(struct rtc_time * tmp)97 int rtc_get (struct rtc_time *tmp)
98 {
99 int rel = 0;
100 uchar sec, min, hour, mday, wday, mon, year;
101
102 #ifdef CONFIG_RTC_MCP79411
103 read_rtc:
104 #endif
105 sec = rtc_read (RTC_SEC_REG_ADDR);
106 min = rtc_read (RTC_MIN_REG_ADDR);
107 hour = rtc_read (RTC_HR_REG_ADDR);
108 wday = rtc_read (RTC_DAY_REG_ADDR);
109 mday = rtc_read (RTC_DATE_REG_ADDR);
110 mon = rtc_read (RTC_MON_REG_ADDR);
111 year = rtc_read (RTC_YR_REG_ADDR);
112
113 DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
114 "hr: %02x min: %02x sec: %02x\n",
115 year, mon, mday, wday, hour, min, sec);
116
117 #ifdef CONFIG_RTC_DS1307
118 if (sec & RTC_SEC_BIT_CH) {
119 printf ("### Warning: RTC oscillator has stopped\n");
120 /* clear the CH flag */
121 rtc_write (RTC_SEC_REG_ADDR,
122 rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
123 rel = -1;
124 }
125 #endif
126
127 #ifdef CONFIG_RTC_MCP79411
128 /* make sure that the backup battery is enabled */
129 if (!(wday & MCP7941X_BIT_VBATEN)) {
130 rtc_write(RTC_DAY_REG_ADDR,
131 wday | MCP7941X_BIT_VBATEN);
132 }
133
134 /* clock halted? turn it on, so clock can tick. */
135 if (!(sec & MCP7941X_BIT_ST)) {
136 rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
137 printf("Started RTC\n");
138 goto read_rtc;
139 }
140 #endif
141
142 tmp->tm_sec = bcd2bin (sec & 0x7F);
143 tmp->tm_min = bcd2bin (min & 0x7F);
144 tmp->tm_hour = bcd2bin (hour & 0x3F);
145 tmp->tm_mday = bcd2bin (mday & 0x3F);
146 tmp->tm_mon = bcd2bin (mon & 0x1F);
147 tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
148 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
149 tmp->tm_yday = 0;
150 tmp->tm_isdst= 0;
151
152 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
153 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
154 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
155
156 return rel;
157 }
158
159 /*
160 * Set the RTC
161 */
rtc_set(struct rtc_time * tmp)162 int rtc_set (struct rtc_time *tmp)
163 {
164 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
165 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
166 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
167
168 if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
169 printf("WARNING: year should be between 1970 and 2069!\n");
170
171 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
172 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
173 #ifdef CONFIG_RTC_MCP79411
174 rtc_write (RTC_DAY_REG_ADDR,
175 bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
176 #else
177 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
178 #endif
179 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
180 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
181 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
182 #ifdef CONFIG_RTC_MCP79411
183 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
184 #else
185 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
186 #endif
187
188 return 0;
189 }
190
191 /*
192 * Reset the RTC. We setting the date back to 1970-01-01.
193 * We also enable the oscillator output on the SQW/OUT pin and program
194 * it for 32,768 Hz output. Note that according to the datasheet, turning
195 * on the square wave output increases the current drain on the backup
196 * battery to something between 480nA and 800nA.
197 */
rtc_reset(void)198 void rtc_reset (void)
199 {
200 rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
201 rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
202 }
203
204 /*
205 * Helper functions
206 */
207
208 static
rtc_read(uchar reg)209 uchar rtc_read (uchar reg)
210 {
211 return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
212 }
213
rtc_write(uchar reg,uchar val)214 static void rtc_write (uchar reg, uchar val)
215 {
216 i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
217 }
218
219 #endif /* !CONFIG_DM_RTC */
220
221 #ifdef CONFIG_DM_RTC
ds1307_rtc_set(struct udevice * dev,const struct rtc_time * tm)222 static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm)
223 {
224 int ret;
225 uchar buf[7];
226 enum ds_type type = dev_get_driver_data(dev);
227
228 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
229 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
230 tm->tm_hour, tm->tm_min, tm->tm_sec);
231
232 if (tm->tm_year < 1970 || tm->tm_year > 2069)
233 printf("WARNING: year should be between 1970 and 2069!\n");
234
235 buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
236 buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
237 buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
238 buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
239 buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
240 buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
241 buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
242
243 if (type == mcp794xx) {
244 buf[RTC_DAY_REG_ADDR] |= MCP7941X_BIT_VBATEN;
245 buf[RTC_SEC_REG_ADDR] |= MCP7941X_BIT_ST;
246 }
247
248 ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
249 if (ret < 0)
250 return ret;
251
252 if (type == ds_1337) {
253 /* Ensure oscillator is enabled */
254 dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR, 0);
255 }
256
257 return 0;
258 }
259
ds1307_rtc_get(struct udevice * dev,struct rtc_time * tm)260 static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm)
261 {
262 int ret;
263 uchar buf[7];
264 enum ds_type type = dev_get_driver_data(dev);
265
266 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
267 if (ret < 0)
268 return ret;
269
270 if (type == ds_1337 || type == ds_1340) {
271 uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR :
272 DS1340_STAT_REG_ADDR;
273 int status = dm_i2c_reg_read(dev, reg);
274
275 if (status >= 0 && (status & RTC_STAT_BIT_OSF)) {
276 printf("### Warning: RTC oscillator has stopped\n");
277 /* clear the OSF flag */
278 dm_i2c_reg_write(dev, reg, status & ~RTC_STAT_BIT_OSF);
279 }
280 }
281
282 tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
283 tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
284 tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
285 tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
286 tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
287 tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) +
288 (bcd2bin(buf[RTC_YR_REG_ADDR]) >= 70 ?
289 1900 : 2000);
290 tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] - 1) & 0x07);
291 tm->tm_yday = 0;
292 tm->tm_isdst = 0;
293
294 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
295 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
296 tm->tm_hour, tm->tm_min, tm->tm_sec);
297
298 return 0;
299 }
300
ds1307_rtc_reset(struct udevice * dev)301 static int ds1307_rtc_reset(struct udevice *dev)
302 {
303 int ret;
304 enum ds_type type = dev_get_driver_data(dev);
305
306 /*
307 * reset clock/oscillator in the seconds register:
308 * on DS1307 bit 7 enables Clock Halt (CH),
309 * on DS1340 bit 7 disables the oscillator (not EOSC)
310 * on MCP794xx bit 7 enables Start Oscillator (ST)
311 */
312 ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
313 if (ret < 0)
314 return ret;
315
316 if (type == ds_1307) {
317 /* Write control register in order to enable square-wave
318 * output (SQWE) and set a default rate of 32.768kHz (RS1|RS0).
319 */
320 ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
321 RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
322 RTC_CTL_BIT_RS0);
323 } else if (type == ds_1337) {
324 /* Write control register in order to enable oscillator output
325 * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1).
326 */
327 ret = dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR,
328 DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1);
329 } else if (type == ds_1340 || type == mcp794xx || type == m41t11) {
330 /* Reset clock calibration, frequency test and output level. */
331 ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0x00);
332 }
333
334 return ret;
335 }
336
ds1307_probe(struct udevice * dev)337 static int ds1307_probe(struct udevice *dev)
338 {
339 i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
340 DM_I2C_CHIP_WR_ADDRESS);
341
342 return 0;
343 }
344
345 static const struct rtc_ops ds1307_rtc_ops = {
346 .get = ds1307_rtc_get,
347 .set = ds1307_rtc_set,
348 .reset = ds1307_rtc_reset,
349 };
350
351 static const struct udevice_id ds1307_rtc_ids[] = {
352 { .compatible = "dallas,ds1307", .data = ds_1307 },
353 { .compatible = "dallas,ds1337", .data = ds_1337 },
354 { .compatible = "dallas,ds1339", .data = ds_1339 },
355 { .compatible = "dallas,ds1340", .data = ds_1340 },
356 { .compatible = "microchip,mcp7940x", .data = mcp794xx },
357 { .compatible = "microchip,mcp7941x", .data = mcp794xx },
358 { .compatible = "st,m41t11", .data = m41t11 },
359 { }
360 };
361
362 U_BOOT_DRIVER(rtc_ds1307) = {
363 .name = "rtc-ds1307",
364 .id = UCLASS_RTC,
365 .probe = ds1307_probe,
366 .of_match = ds1307_rtc_ids,
367 .ops = &ds1307_rtc_ops,
368 };
369 #endif /* CONFIG_DM_RTC */
370