1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY UCLASS_RTC
7
8 #include <clk.h>
9 #include <dm.h>
10 #include <malloc.h>
11 #include <rtc.h>
12 #include <asm/io.h>
13 #include <dm/device_compat.h>
14 #include <linux/bitops.h>
15 #include <linux/iopoll.h>
16
17 #define STM32_RTC_TR 0x00
18 #define STM32_RTC_DR 0x04
19 #define STM32_RTC_ISR 0x0C
20 #define STM32_RTC_PRER 0x10
21 #define STM32_RTC_CR 0x18
22 #define STM32_RTC_WPR 0x24
23
24 /* STM32_RTC_TR bit fields */
25 #define STM32_RTC_SEC_SHIFT 0
26 #define STM32_RTC_SEC GENMASK(6, 0)
27 #define STM32_RTC_MIN_SHIFT 8
28 #define STM32_RTC_MIN GENMASK(14, 8)
29 #define STM32_RTC_HOUR_SHIFT 16
30 #define STM32_RTC_HOUR GENMASK(21, 16)
31
32 /* STM32_RTC_DR bit fields */
33 #define STM32_RTC_DATE_SHIFT 0
34 #define STM32_RTC_DATE GENMASK(5, 0)
35 #define STM32_RTC_MONTH_SHIFT 8
36 #define STM32_RTC_MONTH GENMASK(12, 8)
37 #define STM32_RTC_WDAY_SHIFT 13
38 #define STM32_RTC_WDAY GENMASK(15, 13)
39 #define STM32_RTC_YEAR_SHIFT 16
40 #define STM32_RTC_YEAR GENMASK(23, 16)
41
42 /* STM32_RTC_CR bit fields */
43 #define STM32_RTC_CR_FMT BIT(6)
44
45 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
46 #define STM32_RTC_ISR_INITS BIT(4)
47 #define STM32_RTC_ISR_RSF BIT(5)
48 #define STM32_RTC_ISR_INITF BIT(6)
49 #define STM32_RTC_ISR_INIT BIT(7)
50
51 /* STM32_RTC_PRER bit fields */
52 #define STM32_RTC_PRER_PRED_S_SHIFT 0
53 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
54 #define STM32_RTC_PRER_PRED_A_SHIFT 16
55 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
56
57 /* STM32_RTC_WPR key constants */
58 #define RTC_WPR_1ST_KEY 0xCA
59 #define RTC_WPR_2ND_KEY 0x53
60 #define RTC_WPR_WRONG_KEY 0xFF
61
62 struct stm32_rtc_priv {
63 fdt_addr_t base;
64 };
65
stm32_rtc_get(struct udevice * dev,struct rtc_time * tm)66 static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
67 {
68 struct stm32_rtc_priv *priv = dev_get_priv(dev);
69 u32 tr, dr;
70
71 tr = readl(priv->base + STM32_RTC_TR);
72 dr = readl(priv->base + STM32_RTC_DR);
73
74 tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
75 tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
76 tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
77
78 tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
79 tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
80 tm->tm_year = 2000 +
81 bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
82 tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
83 tm->tm_yday = 0;
84 tm->tm_isdst = 0;
85
86 dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
87 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
88 tm->tm_hour, tm->tm_min, tm->tm_sec);
89
90 return 0;
91 }
92
stm32_rtc_unlock(struct udevice * dev)93 static void stm32_rtc_unlock(struct udevice *dev)
94 {
95 struct stm32_rtc_priv *priv = dev_get_priv(dev);
96
97 writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
98 writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
99 }
100
stm32_rtc_lock(struct udevice * dev)101 static void stm32_rtc_lock(struct udevice *dev)
102 {
103 struct stm32_rtc_priv *priv = dev_get_priv(dev);
104
105 writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
106 }
107
stm32_rtc_enter_init_mode(struct udevice * dev)108 static int stm32_rtc_enter_init_mode(struct udevice *dev)
109 {
110 struct stm32_rtc_priv *priv = dev_get_priv(dev);
111 u32 isr = readl(priv->base + STM32_RTC_ISR);
112
113 if (!(isr & STM32_RTC_ISR_INITF)) {
114 isr |= STM32_RTC_ISR_INIT;
115 writel(isr, priv->base + STM32_RTC_ISR);
116
117 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
118 isr,
119 (isr & STM32_RTC_ISR_INITF),
120 100000);
121 }
122
123 return 0;
124 }
125
stm32_rtc_wait_sync(struct udevice * dev)126 static int stm32_rtc_wait_sync(struct udevice *dev)
127 {
128 struct stm32_rtc_priv *priv = dev_get_priv(dev);
129 u32 isr = readl(priv->base + STM32_RTC_ISR);
130
131 isr &= ~STM32_RTC_ISR_RSF;
132 writel(isr, priv->base + STM32_RTC_ISR);
133
134 /*
135 * Wait for RSF to be set to ensure the calendar registers are
136 * synchronised, it takes around 2 rtc_ck clock cycles
137 */
138 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
139 isr, (isr & STM32_RTC_ISR_RSF),
140 100000);
141 }
142
stm32_rtc_exit_init_mode(struct udevice * dev)143 static void stm32_rtc_exit_init_mode(struct udevice *dev)
144 {
145 struct stm32_rtc_priv *priv = dev_get_priv(dev);
146 u32 isr = readl(priv->base + STM32_RTC_ISR);
147
148 isr &= ~STM32_RTC_ISR_INIT;
149 writel(isr, priv->base + STM32_RTC_ISR);
150 }
151
stm32_rtc_set_time(struct udevice * dev,u32 time,u32 date)152 static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
153 {
154 struct stm32_rtc_priv *priv = dev_get_priv(dev);
155 int ret;
156
157 stm32_rtc_unlock(dev);
158
159 ret = stm32_rtc_enter_init_mode(dev);
160 if (ret)
161 goto lock;
162
163 writel(time, priv->base + STM32_RTC_TR);
164 writel(date, priv->base + STM32_RTC_DR);
165
166 stm32_rtc_exit_init_mode(dev);
167
168 ret = stm32_rtc_wait_sync(dev);
169
170 lock:
171 stm32_rtc_lock(dev);
172 return ret;
173 }
174
stm32_rtc_set(struct udevice * dev,const struct rtc_time * tm)175 static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
176 {
177 u32 t, d;
178
179 dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
180 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
181 tm->tm_hour, tm->tm_min, tm->tm_sec);
182
183 if (tm->tm_year < 2000 || tm->tm_year > 2099)
184 return -EINVAL;
185
186 /* Time in BCD format */
187 t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
188 t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
189 t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
190
191 /* Date in BCD format */
192 d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
193 d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
194 d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
195 STM32_RTC_YEAR;
196 d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
197
198 return stm32_rtc_set_time(dev, t, d);
199 }
200
stm32_rtc_reset(struct udevice * dev)201 static int stm32_rtc_reset(struct udevice *dev)
202 {
203 dev_dbg(dev, "Reset DATE\n");
204
205 return stm32_rtc_set_time(dev, 0, 0);
206 }
207
stm32_rtc_init(struct udevice * dev)208 static int stm32_rtc_init(struct udevice *dev)
209 {
210 struct stm32_rtc_priv *priv = dev_get_priv(dev);
211 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
212 unsigned int rate;
213 struct clk clk;
214 int ret;
215 u32 isr = readl(priv->base + STM32_RTC_ISR);
216
217 if (isr & STM32_RTC_ISR_INITS)
218 return 0;
219
220 ret = clk_get_by_index(dev, 1, &clk);
221 if (ret)
222 return ret;
223
224 ret = clk_enable(&clk);
225 if (ret)
226 return ret;
227
228 rate = clk_get_rate(&clk);
229
230 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
231 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
232 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
233
234 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
235 pred_s = (rate / (pred_a + 1)) - 1;
236
237 if (((pred_s + 1) * (pred_a + 1)) == rate)
238 break;
239 }
240
241 /*
242 * Can't find a 1Hz, so give priority to RTC power consumption
243 * by choosing the higher possible value for prediv_a
244 */
245 if (pred_s > pred_s_max || pred_a > pred_a_max) {
246 pred_a = pred_a_max;
247 pred_s = (rate / (pred_a + 1)) - 1;
248 }
249
250 stm32_rtc_unlock(dev);
251
252 ret = stm32_rtc_enter_init_mode(dev);
253 if (ret) {
254 dev_err(dev,
255 "Can't enter in init mode. Prescaler config failed.\n");
256 goto unlock;
257 }
258
259 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
260 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
261 writel(prer, priv->base + STM32_RTC_PRER);
262
263 /* Force 24h time format */
264 cr = readl(priv->base + STM32_RTC_CR);
265 cr &= ~STM32_RTC_CR_FMT;
266 writel(cr, priv->base + STM32_RTC_CR);
267
268 stm32_rtc_exit_init_mode(dev);
269
270 ret = stm32_rtc_wait_sync(dev);
271
272 unlock:
273 stm32_rtc_lock(dev);
274
275 if (ret)
276 clk_disable(&clk);
277
278 return ret;
279 }
280
stm32_rtc_probe(struct udevice * dev)281 static int stm32_rtc_probe(struct udevice *dev)
282 {
283 struct stm32_rtc_priv *priv = dev_get_priv(dev);
284 struct clk clk;
285 int ret;
286
287 priv->base = dev_read_addr(dev);
288 if (priv->base == FDT_ADDR_T_NONE)
289 return -EINVAL;
290
291 ret = clk_get_by_index(dev, 0, &clk);
292 if (ret)
293 return ret;
294
295 ret = clk_enable(&clk);
296 if (ret)
297 return ret;
298
299 ret = stm32_rtc_init(dev);
300
301 if (ret)
302 clk_disable(&clk);
303
304 return ret;
305 }
306
307 static const struct rtc_ops stm32_rtc_ops = {
308 .get = stm32_rtc_get,
309 .set = stm32_rtc_set,
310 .reset = stm32_rtc_reset,
311 };
312
313 static const struct udevice_id stm32_rtc_ids[] = {
314 { .compatible = "st,stm32mp1-rtc" },
315 { }
316 };
317
318 U_BOOT_DRIVER(rtc_stm32) = {
319 .name = "rtc-stm32",
320 .id = UCLASS_RTC,
321 .probe = stm32_rtc_probe,
322 .of_match = stm32_rtc_ids,
323 .ops = &stm32_rtc_ops,
324 .priv_auto = sizeof(struct stm32_rtc_priv),
325 };
326