1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021, Xilinx, Inc.
4 */
5
6 #define LOG_CATEGORY UCLASS_RTC
7
8 #include <dm.h>
9 #include <rtc.h>
10 #include <asm/io.h>
11
12 /* RTC Registers */
13 #define RTC_SET_TM_WR 0x00
14 #define RTC_SET_TM_RD 0x04
15 #define RTC_CALIB_WR 0x08
16 #define RTC_CUR_TM 0x10
17 #define RTC_INT_STS 0x20
18 #define RTC_CTRL 0x40
19
20 #define RTC_INT_SEC BIT(0)
21 #define RTC_BATT_EN BIT(31)
22 #define RTC_CALIB_DEF 0x198233
23 #define RTC_CALIB_MASK 0x1FFFFF
24
25 struct zynqmp_rtc_priv {
26 fdt_addr_t base;
27 unsigned int calibval;
28 };
29
zynqmp_rtc_get(struct udevice * dev,struct rtc_time * tm)30 static int zynqmp_rtc_get(struct udevice *dev, struct rtc_time *tm)
31 {
32 struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
33 u32 status;
34 unsigned long read_time;
35
36 status = readl(priv->base + RTC_INT_STS);
37
38 if (status & RTC_INT_SEC) {
39 /*
40 * RTC has updated the CURRENT_TIME with the time written into
41 * SET_TIME_WRITE register.
42 */
43 read_time = readl(priv->base + RTC_CUR_TM);
44 } else {
45 /*
46 * Time written in SET_TIME_WRITE has not yet updated into
47 * the seconds read register, so read the time from the
48 * SET_TIME_WRITE instead of CURRENT_TIME register.
49 * Since we add +1 sec while writing, we need to -1 sec while
50 * reading.
51 */
52 read_time = readl(priv->base + RTC_SET_TM_RD) - 1;
53 }
54
55 rtc_to_tm(read_time, tm);
56
57 return 0;
58 }
59
zynqmp_rtc_set(struct udevice * dev,const struct rtc_time * tm)60 static int zynqmp_rtc_set(struct udevice *dev, const struct rtc_time *tm)
61 {
62 struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
63 unsigned long new_time = 0;
64
65 if (tm)
66 /*
67 * The value written will be updated after 1 sec into the
68 * seconds read register, so we need to program time +1 sec
69 * to get the correct time on read.
70 */
71 new_time = rtc_mktime(tm) + 1;
72
73 /*
74 * Writing into calibration register will clear the Tick Counter and
75 * force the next second to be signaled exactly in 1 second period
76 */
77 priv->calibval &= RTC_CALIB_MASK;
78 writel(priv->calibval, (priv->base + RTC_CALIB_WR));
79
80 writel(new_time, priv->base + RTC_SET_TM_WR);
81
82 /*
83 * Clear the rtc interrupt status register after setting the
84 * time. During a read_time function, the code should read the
85 * RTC_INT_STATUS register and if bit 0 is still 0, it means
86 * that one second has not elapsed yet since RTC was set and
87 * the current time should be read from SET_TIME_READ register;
88 * otherwise, CURRENT_TIME register is read to report the time
89 */
90 writel(RTC_INT_SEC, priv->base + RTC_INT_STS);
91
92 return 0;
93 }
94
zynqmp_rtc_reset(struct udevice * dev)95 static int zynqmp_rtc_reset(struct udevice *dev)
96 {
97 return zynqmp_rtc_set(dev, NULL);
98 }
99
zynqmp_rtc_init(struct udevice * dev)100 static int zynqmp_rtc_init(struct udevice *dev)
101 {
102 struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
103 u32 rtc_ctrl;
104
105 /* Enable RTC switch to battery when VCC_PSAUX is not available */
106 rtc_ctrl = readl(priv->base + RTC_CTRL);
107 rtc_ctrl |= RTC_BATT_EN;
108 writel(rtc_ctrl, priv->base + RTC_CTRL);
109
110 /*
111 * Based on crystal freq of 33.330 KHz
112 * set the seconds counter and enable, set fractions counter
113 * to default value suggested as per design spec
114 * to correct RTC delay in frequency over period of time.
115 */
116 priv->calibval &= RTC_CALIB_MASK;
117 writel(priv->calibval, (priv->base + RTC_CALIB_WR));
118
119 return 0;
120 }
121
zynqmp_rtc_probe(struct udevice * dev)122 static int zynqmp_rtc_probe(struct udevice *dev)
123 {
124 struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
125 int ret;
126
127 priv->base = dev_read_addr(dev);
128 if (priv->base == FDT_ADDR_T_NONE)
129 return -EINVAL;
130
131 priv->calibval = dev_read_u32_default(dev, "calibration",
132 RTC_CALIB_DEF);
133
134 ret = zynqmp_rtc_init(dev);
135
136 return ret;
137 }
138
139 static const struct rtc_ops zynqmp_rtc_ops = {
140 .get = zynqmp_rtc_get,
141 .set = zynqmp_rtc_set,
142 .reset = zynqmp_rtc_reset,
143 };
144
145 static const struct udevice_id zynqmp_rtc_ids[] = {
146 { .compatible = "xlnx,zynqmp-rtc" },
147 { }
148 };
149
150 U_BOOT_DRIVER(rtc_zynqmp) = {
151 .name = "rtc-zynqmp",
152 .id = UCLASS_RTC,
153 .probe = zynqmp_rtc_probe,
154 .of_match = zynqmp_rtc_ids,
155 .ops = &zynqmp_rtc_ops,
156 .priv_auto = sizeof(struct zynqmp_rtc_priv),
157 };
158