1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2017 Intel Corporation
4 */
5
6 #include <dm.h>
7 #include <ns16550.h>
8 #include <serial.h>
9
10 /*
11 * The UART clock is calculated as
12 *
13 * UART clock = XTAL * UART_MUL / UART_DIV
14 *
15 * The baudrate is calculated as
16 *
17 * baud rate = UART clock / UART_PS / DLAB
18 */
19 #define UART_PS 0x30
20 #define UART_MUL 0x34
21 #define UART_DIV 0x38
22
mid_writel(struct ns16550_plat * plat,int offset,int value)23 static void mid_writel(struct ns16550_plat *plat, int offset, int value)
24 {
25 unsigned char *addr;
26
27 offset *= 1 << plat->reg_shift;
28 addr = (unsigned char *)plat->base + offset;
29
30 writel(value, addr + plat->reg_offset);
31 }
32
mid_serial_probe(struct udevice * dev)33 static int mid_serial_probe(struct udevice *dev)
34 {
35 struct ns16550_plat *plat = dev_get_plat(dev);
36
37 /*
38 * Initialize fractional divider correctly for Intel Edison
39 * platform.
40 *
41 * For backward compatibility we have to set initial DLAB value
42 * to 16 and speed to 115200 baud, where initial frequency is
43 * 29491200Hz, and XTAL frequency is 38.4MHz.
44 */
45 mid_writel(plat, UART_MUL, 96);
46 mid_writel(plat, UART_DIV, 125);
47 mid_writel(plat, UART_PS, 16);
48
49 return ns16550_serial_probe(dev);
50 }
51
52 static const struct udevice_id mid_serial_ids[] = {
53 { .compatible = "intel,mid-uart" },
54 {}
55 };
56
57 U_BOOT_DRIVER(serial_intel_mid) = {
58 .name = "serial_intel_mid",
59 .id = UCLASS_SERIAL,
60 .of_match = mid_serial_ids,
61 .of_to_plat = ns16550_serial_of_to_plat,
62 .plat_auto = sizeof(struct ns16550_plat),
63 .priv_auto = sizeof(struct ns16550),
64 .probe = mid_serial_probe,
65 .ops = &ns16550_serial_ops,
66 };
67