1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <command.h>
8 #include <dm.h>
9 #include <serial.h>
10 #include <watchdog.h>
11 #include <asm/cpm_8xx.h>
12 #include <asm/global_data.h>
13 #include <linux/compiler.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
18 #define SMC_INDEX 0
19 #define PROFF_SMC PROFF_SMC1
20 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
21 #define IOPINS 0xc0
22
23 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
24 #define SMC_INDEX 1
25 #define PROFF_SMC PROFF_SMC2
26 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
27 #define IOPINS 0xc00
28
29 #endif /* CONFIG_8xx_CONS_SMCx */
30
31 struct serialbuffer {
32 cbd_t rxbd; /* Rx BD */
33 cbd_t txbd; /* Tx BD */
34 uint rxindex; /* index for next character to read */
35 uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
36 uchar txbuf; /* tx buffers */
37 };
38
serial_setdivisor(cpm8xx_t __iomem * cp,int baudrate)39 static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
40 {
41 int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;
42
43 if (divisor / 16 > 0x1000) {
44 /* bad divisor, assume 50MHz clock and 9600 baud */
45 divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
46 }
47
48 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
49
50 if (divisor <= 0x1000)
51 out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
52 else
53 out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
54 CPM_BRG_DIV16);
55 }
56
57 /*
58 * Minimal serial functions needed to use one of the SMC ports
59 * as serial console interface.
60 */
61
serial_mpc8xx_setbrg(struct udevice * dev,int baudrate)62 static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
63 {
64 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
65 cpm8xx_t __iomem *cp = &(im->im_cpm);
66
67 /* Set up the baud rate generator.
68 * See 8xx_io/commproc.c for details.
69 *
70 * Wire BRG1 to SMCx
71 */
72
73 out_be32(&cp->cp_simode, 0);
74
75 serial_setdivisor(cp, baudrate);
76
77 return 0;
78 }
79
serial_mpc8xx_probe(struct udevice * dev)80 static int serial_mpc8xx_probe(struct udevice *dev)
81 {
82 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
83 smc_t __iomem *sp;
84 smc_uart_t __iomem *up;
85 u16 smc_rpbase;
86 cpm8xx_t __iomem *cp = &(im->im_cpm);
87 struct serialbuffer __iomem *rtx;
88
89 /* initialize pointers to SMC */
90
91 sp = cp->cp_smc + SMC_INDEX;
92 up = (smc_uart_t __iomem *)&cp->cp_dpmem[PROFF_SMC];
93
94 smc_rpbase = in_be16(&up->smc_rpbase);
95 if (smc_rpbase)
96 up = (smc_uart_t __iomem *)&cp->cp_dpmem[smc_rpbase];
97
98 /* Disable transmitter/receiver. */
99 clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
100
101 /* Enable SDMA. */
102 out_be32(&im->im_siu_conf.sc_sdcr, 1);
103
104 /* clear error conditions */
105 out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
106
107 /* clear SDMA interrupt mask */
108 out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
109
110 /* Use Port B for SMCx instead of other functions. */
111 setbits_be32(&cp->cp_pbpar, IOPINS);
112 clrbits_be32(&cp->cp_pbdir, IOPINS);
113 clrbits_be16(&cp->cp_pbodr, IOPINS);
114
115 /* Set the physical address of the host memory buffers in
116 * the buffer descriptors.
117 */
118 rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
119 /* Allocate space for two buffer descriptors in the DP ram.
120 * For now, this address seems OK, but it may have to
121 * change with newer versions of the firmware.
122 * damm: allocating space after the two buffers for rx/tx data
123 */
124
125 out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
126 out_be16(&rtx->rxbd.cbd_sc, 0);
127
128 out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
129 out_be16(&rtx->txbd.cbd_sc, 0);
130
131 /* Set up the uart parameters in the parameter ram. */
132 out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
133 out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
134 out_8(&up->smc_rfcr, SMC_EB);
135 out_8(&up->smc_tfcr, SMC_EB);
136
137 /* Set UART mode, 8 bit, no parity, one stop.
138 * Enable receive and transmit.
139 */
140 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
141
142 /* Mask all interrupts and remove anything pending.
143 */
144 out_8(&sp->smc_smcm, 0);
145 out_8(&sp->smc_smce, 0xff);
146
147 /* Set up the baud rate generator */
148 serial_mpc8xx_setbrg(dev, gd->baudrate);
149
150 /* Make the first buffer the only buffer. */
151 setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
152 setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
153
154 /* single/multi character receive. */
155 out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
156 out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
157 out_be32(&rtx->rxindex, 0);
158
159 out_be32(&up->smc_rstate, 0);
160 out_be32(&up->smc_tstate, 0);
161 out_be16(&up->smc_rbptr, CPM_SERIAL_BASE);
162 out_be16(&up->smc_tbptr, CPM_SERIAL_BASE + sizeof(cbd_t));
163 out_be16(&up->smc_brkcr, 1);
164 out_be16(&up->smc_brkec, 0);
165
166 /* Enable transmitter/receiver. */
167 setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
168
169 return 0;
170 }
171
serial_mpc8xx_putc(struct udevice * dev,const char c)172 static int serial_mpc8xx_putc(struct udevice *dev, const char c)
173 {
174 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
175 cpm8xx_t __iomem *cpmp = &(im->im_cpm);
176 struct serialbuffer __iomem *rtx;
177
178 rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
179
180 if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
181 return -EAGAIN;
182
183 out_8(&rtx->txbuf, c);
184 out_be16(&rtx->txbd.cbd_datlen, 1);
185 setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
186
187 return 0;
188 }
189
serial_mpc8xx_getc(struct udevice * dev)190 static int serial_mpc8xx_getc(struct udevice *dev)
191 {
192 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
193 cpm8xx_t __iomem *cpmp = &(im->im_cpm);
194 struct serialbuffer __iomem *rtx;
195 unsigned char c;
196 uint rxindex;
197
198 rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
199
200 if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
201 return -EAGAIN;
202
203 /* the characters are read one by one,
204 * use the rxindex to know the next char to deliver
205 */
206 rxindex = in_be32(&rtx->rxindex);
207 c = in_8(rtx->rxbuf + rxindex);
208 rxindex++;
209
210 /* check if all char are readout, then make prepare for next receive */
211 if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
212 rxindex = 0;
213 setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
214 }
215 out_be32(&rtx->rxindex, rxindex);
216 return c;
217 }
218
serial_mpc8xx_pending(struct udevice * dev,bool input)219 static int serial_mpc8xx_pending(struct udevice *dev, bool input)
220 {
221 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
222 cpm8xx_t __iomem *cpmp = &(im->im_cpm);
223 struct serialbuffer __iomem *rtx;
224
225 if (!input)
226 return 0;
227
228 rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
229
230 return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
231 }
232
233 static const struct dm_serial_ops serial_mpc8xx_ops = {
234 .putc = serial_mpc8xx_putc,
235 .pending = serial_mpc8xx_pending,
236 .getc = serial_mpc8xx_getc,
237 .setbrg = serial_mpc8xx_setbrg,
238 };
239
240 static const struct udevice_id serial_mpc8xx_ids[] = {
241 { .compatible = "fsl,pq1-smc" },
242 { }
243 };
244
245 U_BOOT_DRIVER(serial_mpc8xx) = {
246 .name = "serial_mpc8xx",
247 .id = UCLASS_SERIAL,
248 .of_match = serial_mpc8xx_ids,
249 .probe = serial_mpc8xx_probe,
250 .ops = &serial_mpc8xx_ops,
251 .flags = DM_FLAG_PRE_RELOC,
252 };
253