1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek High-speed UART driver
4  *
5  * Copyright (C) 2018 MediaTek Inc.
6  * Author: Weijie Gao <weijie.gao@mediatek.com>
7  */
8 
9 #include <clk.h>
10 #include <config.h>
11 #include <div64.h>
12 #include <dm.h>
13 #include <dm/device.h>
14 #include <dm/device_compat.h>
15 #include <errno.h>
16 #include <log.h>
17 #include <serial.h>
18 #include <watchdog.h>
19 #include <asm/global_data.h>
20 #include <asm/io.h>
21 #include <asm/types.h>
22 #include <linux/err.h>
23 #include <linux/printk.h>
24 
25 struct mtk_serial_regs {
26 	u32 rbr;
27 	u32 ier;
28 	u32 fcr;
29 	u32 lcr;
30 	u32 mcr;
31 	u32 lsr;
32 	u32 msr;
33 	u32 scr;
34 	u32 autobaud_en;
35 	u32 highspeed;
36 	u32 sample_count;
37 	u32 sample_point;
38 	u32 autobaud_reg;
39 	u32 ratefix_ad;
40 	u32 autobaud_sample;
41 	u32 guard;
42 	u32 escape_dat;
43 	u32 escape_en;
44 	u32 sleep_en;
45 	u32 dma_en;
46 	u32 rxtri_ad;
47 	u32 fracdiv_l;
48 	u32 fracdiv_m;
49 	u32 fcr_rd;
50 };
51 
52 #define thr rbr
53 #define iir fcr
54 #define dll rbr
55 #define dlm ier
56 
57 #define UART_LCR_WLS_8	0x03		/* 8 bit character length */
58 #define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
59 
60 #define UART_LSR_DR	0x01		/* Data ready */
61 #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
62 #define UART_LSR_TEMT	0x40		/* Xmitter empty */
63 
64 #define UART_MCR_DTR	0x01		/* DTR   */
65 #define UART_MCR_RTS	0x02		/* RTS   */
66 
67 #define UART_FCR_FIFO_EN	0x01	/* Fifo enable */
68 #define UART_FCR_RXSR		0x02	/* Receiver soft reset */
69 #define UART_FCR_TXSR		0x04	/* Transmitter soft reset */
70 
71 #define UART_MCRVAL (UART_MCR_DTR | \
72 		     UART_MCR_RTS)
73 
74 /* Clear & enable FIFOs */
75 #define UART_FCRVAL (UART_FCR_FIFO_EN | \
76 		     UART_FCR_RXSR |	\
77 		     UART_FCR_TXSR)
78 
79 /* the data is correct if the real baud is within 3%. */
80 #define BAUD_ALLOW_MAX(baud)	((baud) + (baud) * 3 / 100)
81 #define BAUD_ALLOW_MIX(baud)	((baud) - (baud) * 3 / 100)
82 
83 /* struct mtk_serial_priv -	Structure holding all information used by the
84  *				driver
85  * @regs:			Register base of the serial port
86  * @clk:			The baud clock device
87  * @clk_bus:			The bus clock device
88  * @fixed_clk_rate:		Fallback fixed baud clock rate if baud clock
89  *				device is not specified
90  * @force_highspeed:		Force using high-speed mode
91  * @upstream_highspeed_logic:	Apply upstream high-speed logic
92  */
93 struct mtk_serial_priv {
94 	struct mtk_serial_regs __iomem *regs;
95 	struct clk clk;
96 	struct clk clk_bus;
97 	u32 fixed_clk_rate;
98 	bool force_highspeed;
99 	bool upstream_highspeed_logic;
100 };
101 
102 static const unsigned short fraction_l_mapping[] = {
103 	0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
104 };
105 
106 static const unsigned short fraction_m_mapping[] = {
107 	0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
108 };
109 
_mtk_serial_setbrg(struct mtk_serial_priv * priv,int baud,uint clk_rate)110 static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
111 			       uint clk_rate)
112 {
113 	u32 quot, realbaud, samplecount = 1, fraction, frac_l = 0, frac_m = 0;
114 
115 	/* Special case for low baud clock */
116 	if (baud <= 115200 && clk_rate == 12000000) {
117 		writel(3, &priv->regs->highspeed);
118 
119 		quot = DIV_ROUND_CLOSEST(clk_rate, 256 * baud);
120 		if (quot == 0)
121 			quot = 1;
122 
123 		samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
124 
125 		realbaud = clk_rate / samplecount / quot;
126 		if (realbaud > BAUD_ALLOW_MAX(baud) ||
127 		    realbaud < BAUD_ALLOW_MIX(baud)) {
128 			pr_info("baud %d can't be handled\n", baud);
129 		}
130 
131 		goto set_baud;
132 	}
133 
134 	/*
135 	 * Upstream linux use highspeed for anything >= 115200 and lowspeed
136 	 * for < 115200. Simulate this if we are using the upstream compatible.
137 	 */
138 	if (priv->force_highspeed ||
139 	    (priv->upstream_highspeed_logic && baud >= 115200))
140 		goto use_hs3;
141 
142 	if (baud <= 115200) {
143 		writel(0, &priv->regs->highspeed);
144 		quot = DIV_ROUND_CLOSEST(clk_rate, 16 * baud);
145 	} else if (baud <= 576000) {
146 		writel(2, &priv->regs->highspeed);
147 
148 		/* Set to next lower baudrate supported */
149 		if ((baud == 500000) || (baud == 576000))
150 			baud = 460800;
151 
152 		quot = DIV_ROUND_UP(clk_rate, 4 * baud);
153 	} else {
154 use_hs3:
155 		writel(3, &priv->regs->highspeed);
156 
157 		quot = DIV_ROUND_UP(clk_rate, 256 * baud);
158 		samplecount = clk_rate / (quot * baud);
159 
160 		fraction = ((clk_rate * 100) / quot / baud) % 100;
161 		fraction = DIV_ROUND_CLOSEST(fraction, 10);
162 
163 		frac_l = fraction_l_mapping[fraction];
164 		frac_m = fraction_m_mapping[fraction];
165 	}
166 
167 set_baud:
168 	/* set divisor */
169 	writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
170 	writel(quot & 0xff, &priv->regs->dll);
171 	writel((quot >> 8) & 0xff, &priv->regs->dlm);
172 	writel(UART_LCR_WLS_8, &priv->regs->lcr);
173 
174 	/* set highspeed mode sample count & point */
175 	writel(samplecount - 1, &priv->regs->sample_count);
176 	writel((samplecount >> 1) - 1, &priv->regs->sample_point);
177 
178 	/* set baudrate fraction compensation */
179 	writel(frac_l, &priv->regs->fracdiv_l);
180 	writel(frac_m, &priv->regs->fracdiv_m);
181 }
182 
_mtk_serial_putc(struct mtk_serial_priv * priv,const char ch)183 static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
184 {
185 	if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
186 		return -EAGAIN;
187 
188 	writel(ch, &priv->regs->thr);
189 
190 	if (ch == '\n')
191 		schedule();
192 
193 	return 0;
194 }
195 
_mtk_serial_getc(struct mtk_serial_priv * priv)196 static int _mtk_serial_getc(struct mtk_serial_priv *priv)
197 {
198 	if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
199 		return -EAGAIN;
200 
201 	return readl(&priv->regs->rbr);
202 }
203 
_mtk_serial_pending(struct mtk_serial_priv * priv,bool input)204 static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
205 {
206 	if (input)
207 		return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
208 	else
209 		return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
210 }
211 
212 #if CONFIG_IS_ENABLED(DM_SERIAL)
mtk_serial_setbrg(struct udevice * dev,int baudrate)213 static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
214 {
215 	struct mtk_serial_priv *priv = dev_get_priv(dev);
216 	u32 clk_rate;
217 
218 	clk_rate = clk_get_rate(&priv->clk);
219 	if (IS_ERR_VALUE(clk_rate) || clk_rate == 0)
220 		clk_rate = priv->fixed_clk_rate;
221 
222 	_mtk_serial_setbrg(priv, baudrate, clk_rate);
223 
224 	return 0;
225 }
226 
mtk_serial_putc(struct udevice * dev,const char ch)227 static int mtk_serial_putc(struct udevice *dev, const char ch)
228 {
229 	struct mtk_serial_priv *priv = dev_get_priv(dev);
230 
231 	return _mtk_serial_putc(priv, ch);
232 }
233 
mtk_serial_getc(struct udevice * dev)234 static int mtk_serial_getc(struct udevice *dev)
235 {
236 	struct mtk_serial_priv *priv = dev_get_priv(dev);
237 
238 	return _mtk_serial_getc(priv);
239 }
240 
mtk_serial_pending(struct udevice * dev,bool input)241 static int mtk_serial_pending(struct udevice *dev, bool input)
242 {
243 	struct mtk_serial_priv *priv = dev_get_priv(dev);
244 
245 	return _mtk_serial_pending(priv, input);
246 }
247 
mtk_serial_probe(struct udevice * dev)248 static int mtk_serial_probe(struct udevice *dev)
249 {
250 	struct mtk_serial_priv *priv = dev_get_priv(dev);
251 
252 	/* Disable interrupt */
253 	writel(0, &priv->regs->ier);
254 
255 	writel(UART_MCRVAL, &priv->regs->mcr);
256 	writel(UART_FCRVAL, &priv->regs->fcr);
257 
258 	clk_enable(&priv->clk);
259 	if (priv->clk_bus.dev)
260 		clk_enable(&priv->clk_bus);
261 
262 	return 0;
263 }
264 
mtk_serial_of_to_plat(struct udevice * dev)265 static int mtk_serial_of_to_plat(struct udevice *dev)
266 {
267 	struct mtk_serial_priv *priv = dev_get_priv(dev);
268 	fdt_addr_t addr;
269 	int err;
270 
271 	addr = dev_read_addr(dev);
272 	if (addr == FDT_ADDR_T_NONE)
273 		return -EINVAL;
274 
275 	priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
276 
277 	err = clk_get_by_index(dev, 0, &priv->clk);
278 	if (err) {
279 		err = dev_read_u32(dev, "clock-frequency", &priv->fixed_clk_rate);
280 		if (err) {
281 			dev_err(dev, "baud clock not defined\n");
282 			return -EINVAL;
283 		}
284 	} else {
285 		err = clk_get_rate(&priv->clk);
286 		if (IS_ERR_VALUE(err)) {
287 			dev_err(dev, "invalid baud clock\n");
288 			return -EINVAL;
289 		}
290 	}
291 
292 	clk_get_by_name(dev, "bus", &priv->clk_bus);
293 
294 	priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
295 	priv->upstream_highspeed_logic =
296 		device_is_compatible(dev, "mediatek,mt6577-uart");
297 
298 	return 0;
299 }
300 
301 static const struct dm_serial_ops mtk_serial_ops = {
302 	.putc = mtk_serial_putc,
303 	.pending = mtk_serial_pending,
304 	.getc = mtk_serial_getc,
305 	.setbrg = mtk_serial_setbrg,
306 };
307 
308 static const struct udevice_id mtk_serial_ids[] = {
309 	{ .compatible = "mediatek,hsuart" },
310 	{ .compatible = "mediatek,mt6577-uart" },
311 	{ }
312 };
313 
314 U_BOOT_DRIVER(serial_mtk) = {
315 	.name = "serial_mtk",
316 	.id = UCLASS_SERIAL,
317 	.of_match = mtk_serial_ids,
318 	.of_to_plat = mtk_serial_of_to_plat,
319 	.priv_auto	= sizeof(struct mtk_serial_priv),
320 	.probe = mtk_serial_probe,
321 	.ops = &mtk_serial_ops,
322 	.flags = DM_FLAG_PRE_RELOC,
323 };
324 #else
325 
326 DECLARE_GLOBAL_DATA_PTR;
327 
328 #define DECLARE_HSUART_PRIV(port) \
329 	static struct mtk_serial_priv mtk_hsuart##port = { \
330 	.regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \
331 	.fixed_clk_rate = CFG_SYS_NS16550_CLK \
332 };
333 
334 #define DECLARE_HSUART_FUNCTIONS(port) \
335 	static int mtk_serial##port##_init(void) \
336 	{ \
337 		writel(0, &mtk_hsuart##port.regs->ier); \
338 		writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
339 		writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
340 		_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \
341 				   mtk_hsuart##port.fixed_clk_rate); \
342 		return 0 ; \
343 	} \
344 	static void mtk_serial##port##_setbrg(void) \
345 	{ \
346 		_mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \
347 				   mtk_hsuart##port.fixed_clk_rate); \
348 	} \
349 	static int mtk_serial##port##_getc(void) \
350 	{ \
351 		int err; \
352 		do { \
353 			err = _mtk_serial_getc(&mtk_hsuart##port); \
354 			if (err == -EAGAIN) \
355 				schedule(); \
356 		} while (err == -EAGAIN); \
357 		return err >= 0 ? err : 0; \
358 	} \
359 	static int mtk_serial##port##_tstc(void) \
360 	{ \
361 		return _mtk_serial_pending(&mtk_hsuart##port, true); \
362 	} \
363 	static void mtk_serial##port##_putc(const char c) \
364 	{ \
365 		int err; \
366 		if (c == '\n') \
367 			mtk_serial##port##_putc('\r'); \
368 		do { \
369 			err = _mtk_serial_putc(&mtk_hsuart##port, c); \
370 		} while (err == -EAGAIN); \
371 	} \
372 	static void mtk_serial##port##_puts(const char *s) \
373 	{ \
374 		while (*s) { \
375 			mtk_serial##port##_putc(*s++); \
376 		} \
377 	}
378 
379 /* Serial device descriptor */
380 #define INIT_HSUART_STRUCTURE(port, __name) {	\
381 	.name	= __name,			\
382 	.start	= mtk_serial##port##_init,	\
383 	.stop	= NULL,				\
384 	.setbrg	= mtk_serial##port##_setbrg,	\
385 	.getc	= mtk_serial##port##_getc,	\
386 	.tstc	= mtk_serial##port##_tstc,	\
387 	.putc	= mtk_serial##port##_putc,	\
388 	.puts	= mtk_serial##port##_puts,	\
389 }
390 
391 #define DECLARE_HSUART(port, __name) \
392 	DECLARE_HSUART_PRIV(port); \
393 	DECLARE_HSUART_FUNCTIONS(port); \
394 	struct serial_device mtk_hsuart##port##_device = \
395 		INIT_HSUART_STRUCTURE(port, __name);
396 
397 #if !defined(CONFIG_CONS_INDEX)
398 #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
399 #error	"Invalid console index value."
400 #endif
401 
402 #if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1)
403 #error	"Console port 1 defined but not configured."
404 #elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2)
405 #error	"Console port 2 defined but not configured."
406 #elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3)
407 #error	"Console port 3 defined but not configured."
408 #elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4)
409 #error	"Console port 4 defined but not configured."
410 #elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5)
411 #error	"Console port 5 defined but not configured."
412 #elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6)
413 #error	"Console port 6 defined but not configured."
414 #endif
415 
416 #if defined(CFG_SYS_NS16550_COM1)
417 DECLARE_HSUART(1, "mtk-hsuart0");
418 #endif
419 #if defined(CFG_SYS_NS16550_COM2)
420 DECLARE_HSUART(2, "mtk-hsuart1");
421 #endif
422 #if defined(CFG_SYS_NS16550_COM3)
423 DECLARE_HSUART(3, "mtk-hsuart2");
424 #endif
425 #if defined(CFG_SYS_NS16550_COM4)
426 DECLARE_HSUART(4, "mtk-hsuart3");
427 #endif
428 #if defined(CFG_SYS_NS16550_COM5)
429 DECLARE_HSUART(5, "mtk-hsuart4");
430 #endif
431 #if defined(CFG_SYS_NS16550_COM6)
432 DECLARE_HSUART(6, "mtk-hsuart5");
433 #endif
434 
default_serial_console(void)435 __weak struct serial_device *default_serial_console(void)
436 {
437 #if CONFIG_CONS_INDEX == 1
438 	return &mtk_hsuart1_device;
439 #elif CONFIG_CONS_INDEX == 2
440 	return &mtk_hsuart2_device;
441 #elif CONFIG_CONS_INDEX == 3
442 	return &mtk_hsuart3_device;
443 #elif CONFIG_CONS_INDEX == 4
444 	return &mtk_hsuart4_device;
445 #elif CONFIG_CONS_INDEX == 5
446 	return &mtk_hsuart5_device;
447 #elif CONFIG_CONS_INDEX == 6
448 	return &mtk_hsuart6_device;
449 #else
450 #error "Bad CONFIG_CONS_INDEX."
451 #endif
452 }
453 
mtk_serial_initialize(void)454 void mtk_serial_initialize(void)
455 {
456 #if defined(CFG_SYS_NS16550_COM1)
457 	serial_register(&mtk_hsuart1_device);
458 #endif
459 #if defined(CFG_SYS_NS16550_COM2)
460 	serial_register(&mtk_hsuart2_device);
461 #endif
462 #if defined(CFG_SYS_NS16550_COM3)
463 	serial_register(&mtk_hsuart3_device);
464 #endif
465 #if defined(CFG_SYS_NS16550_COM4)
466 	serial_register(&mtk_hsuart4_device);
467 #endif
468 #if defined(CFG_SYS_NS16550_COM5)
469 	serial_register(&mtk_hsuart5_device);
470 #endif
471 #if defined(CFG_SYS_NS16550_COM6)
472 	serial_register(&mtk_hsuart6_device);
473 #endif
474 }
475 
476 #endif
477 
478 #ifdef CONFIG_DEBUG_UART_MTK
479 
480 #include <debug_uart.h>
481 
_debug_uart_init(void)482 static inline void _debug_uart_init(void)
483 {
484 	struct mtk_serial_priv priv;
485 
486 	memset(&priv, 0, sizeof(struct mtk_serial_priv));
487 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
488 	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
489 
490 	writel(0, &priv.regs->ier);
491 	writel(UART_MCRVAL, &priv.regs->mcr);
492 	writel(UART_FCRVAL, &priv.regs->fcr);
493 
494 	_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE, priv.fixed_clk_rate);
495 }
496 
_debug_uart_putc(int ch)497 static inline void _debug_uart_putc(int ch)
498 {
499 	struct mtk_serial_regs __iomem *regs =
500 		(void *) CONFIG_VAL(DEBUG_UART_BASE);
501 
502 	while (!(readl(&regs->lsr) & UART_LSR_THRE))
503 		;
504 
505 	writel(ch, &regs->thr);
506 }
507 
508 DEBUG_UART_FUNCS
509 
510 #endif
511