1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000
4 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
5 *
6 * (C) Copyright 2004
7 * ARM Ltd.
8 * Philippe Robin, <philippe.robin@arm.com>
9 */
10
11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
12
13 #include <asm/global_data.h>
14 /* For get_bus_freq() */
15 #include <clock_legacy.h>
16 #include <dm.h>
17 #include <clk.h>
18 #include <errno.h>
19 #include <watchdog.h>
20 #include <asm/io.h>
21 #include <serial.h>
22 #include <spl.h>
23 #include <dm/device_compat.h>
24 #include <dm/platform_data/serial_pl01x.h>
25 #include <linux/compiler.h>
26 #include "serial_pl01x_internal.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #if !CONFIG_IS_ENABLED(DM_SERIAL)
31 static volatile unsigned char *const port[] = CFG_PL01x_PORTS;
32 static enum pl01x_type pl01x_type __section(".data");
33 static struct pl01x_regs *base_regs __section(".data");
34 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
35
36 #endif
37
pl01x_putc(struct pl01x_regs * regs,char c)38 static int pl01x_putc(struct pl01x_regs *regs, char c)
39 {
40 /* Wait until there is space in the FIFO */
41 if (readl(®s->fr) & UART_PL01x_FR_TXFF)
42 return -EAGAIN;
43
44 /* Send the character */
45 writel(c, ®s->dr);
46
47 return 0;
48 }
49
pl01x_getc(struct pl01x_regs * regs)50 static int pl01x_getc(struct pl01x_regs *regs)
51 {
52 unsigned int data;
53
54 /* Wait until there is data in the FIFO */
55 if (readl(®s->fr) & UART_PL01x_FR_RXFE)
56 return -EAGAIN;
57
58 data = readl(®s->dr);
59
60 /* Check for an error flag */
61 if (data & 0xFFFFFF00) {
62 /* Clear the error */
63 writel(0xFFFFFFFF, ®s->ecr);
64 return -1;
65 }
66
67 return (int) data;
68 }
69
pl01x_tstc(struct pl01x_regs * regs)70 static int pl01x_tstc(struct pl01x_regs *regs)
71 {
72 schedule();
73 return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
74 }
75
pl01x_generic_serial_init(struct pl01x_regs * regs,enum pl01x_type type)76 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
77 enum pl01x_type type)
78 {
79 switch (type) {
80 case TYPE_PL010:
81 /* disable everything */
82 writel(0, ®s->pl010_cr);
83 break;
84 case TYPE_PL011:
85 /* disable everything */
86 writel(0, ®s->pl011_cr);
87 break;
88 default:
89 return -EINVAL;
90 }
91
92 return 0;
93 }
94
pl011_set_line_control(struct pl01x_regs * regs)95 static int pl011_set_line_control(struct pl01x_regs *regs)
96 {
97 unsigned int lcr;
98 /*
99 * Internal update of baud rate register require line
100 * control register write
101 */
102 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
103 writel(lcr, ®s->pl011_lcrh);
104 return 0;
105 }
106
pl01x_generic_setbrg(struct pl01x_regs * regs,enum pl01x_type type,int clock,int baudrate)107 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
108 int clock, int baudrate)
109 {
110 switch (type) {
111 case TYPE_PL010: {
112 unsigned int divisor;
113
114 /* disable everything */
115 writel(0, ®s->pl010_cr);
116
117 switch (baudrate) {
118 case 9600:
119 divisor = UART_PL010_BAUD_9600;
120 break;
121 case 19200:
122 divisor = UART_PL010_BAUD_19200;
123 break;
124 case 38400:
125 divisor = UART_PL010_BAUD_38400;
126 break;
127 case 57600:
128 divisor = UART_PL010_BAUD_57600;
129 break;
130 case 115200:
131 divisor = UART_PL010_BAUD_115200;
132 break;
133 default:
134 divisor = UART_PL010_BAUD_38400;
135 }
136
137 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
138 writel(divisor & 0xff, ®s->pl010_lcrl);
139
140 /*
141 * Set line control for the PL010 to be 8 bits, 1 stop bit,
142 * no parity, fifo enabled
143 */
144 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
145 ®s->pl010_lcrh);
146 /* Finally, enable the UART */
147 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
148 break;
149 }
150 case TYPE_PL011: {
151 unsigned int temp;
152 unsigned int divider;
153 unsigned int remainder;
154 unsigned int fraction;
155
156 /* Without a valid clock rate we cannot set up the baudrate. */
157 if (clock) {
158 /*
159 * Set baud rate
160 *
161 * IBRD = UART_CLK / (16 * BAUD_RATE)
162 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
163 * / (16 * BAUD_RATE))
164 */
165 temp = 16 * baudrate;
166 divider = clock / temp;
167 remainder = clock % temp;
168 temp = (8 * remainder) / baudrate;
169 fraction = (temp >> 1) + (temp & 1);
170
171 writel(divider, ®s->pl011_ibrd);
172 writel(fraction, ®s->pl011_fbrd);
173 }
174
175 pl011_set_line_control(regs);
176 /* Finally, enable the UART */
177 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
178 UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
179 break;
180 }
181 default:
182 return -EINVAL;
183 }
184
185 return 0;
186 }
187
188 #if !CONFIG_IS_ENABLED(DM_SERIAL)
pl01x_serial_init_baud(int baudrate)189 static void pl01x_serial_init_baud(int baudrate)
190 {
191 int clock = 0;
192
193 #if defined(CONFIG_PL011_SERIAL)
194 pl01x_type = TYPE_PL011;
195 clock = CFG_PL011_CLOCK;
196 #endif
197 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
198
199 pl01x_generic_serial_init(base_regs, pl01x_type);
200 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
201 }
202
203 /*
204 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
205 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
206 * Versatile PB has four UARTs.
207 */
pl01x_serial_init(void)208 int pl01x_serial_init(void)
209 {
210 pl01x_serial_init_baud(CONFIG_BAUDRATE);
211
212 return 0;
213 }
214
pl01x_serial_putc(const char c)215 static void pl01x_serial_putc(const char c)
216 {
217 if (c == '\n')
218 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
219
220 while (pl01x_putc(base_regs, c) == -EAGAIN);
221 }
222
pl01x_serial_getc(void)223 static int pl01x_serial_getc(void)
224 {
225 while (1) {
226 int ch = pl01x_getc(base_regs);
227
228 if (ch == -EAGAIN) {
229 schedule();
230 continue;
231 }
232
233 return ch;
234 }
235 }
236
pl01x_serial_tstc(void)237 static int pl01x_serial_tstc(void)
238 {
239 return pl01x_tstc(base_regs);
240 }
241
pl01x_serial_setbrg(void)242 static void pl01x_serial_setbrg(void)
243 {
244 /*
245 * Flush FIFO and wait for non-busy before changing baudrate to avoid
246 * crap in console
247 */
248 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
249 schedule();
250 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
251 schedule();
252 pl01x_serial_init_baud(gd->baudrate);
253 }
254
255 static struct serial_device pl01x_serial_drv = {
256 .name = "pl01x_serial",
257 .start = pl01x_serial_init,
258 .stop = NULL,
259 .setbrg = pl01x_serial_setbrg,
260 .putc = pl01x_serial_putc,
261 .puts = default_serial_puts,
262 .getc = pl01x_serial_getc,
263 .tstc = pl01x_serial_tstc,
264 };
265
pl01x_serial_initialize(void)266 void pl01x_serial_initialize(void)
267 {
268 serial_register(&pl01x_serial_drv);
269 }
270
default_serial_console(void)271 __weak struct serial_device *default_serial_console(void)
272 {
273 return &pl01x_serial_drv;
274 }
275 #else
276
pl01x_serial_getinfo(struct udevice * dev,struct serial_device_info * info)277 static int pl01x_serial_getinfo(struct udevice *dev,
278 struct serial_device_info *info)
279 {
280 struct pl01x_serial_plat *plat = dev_get_plat(dev);
281
282 /* save code size */
283 if (!not_xpl())
284 return -ENOSYS;
285
286 info->type = SERIAL_CHIP_PL01X;
287 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
288 info->addr = plat->base;
289 info->size = 0x1000;
290 info->reg_width = 4;
291 info->reg_shift = 2;
292 info->reg_offset = 0;
293 info->clock = plat->clock;
294
295 return 0;
296 }
297
pl01x_serial_setbrg(struct udevice * dev,int baudrate)298 int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
299 {
300 struct pl01x_serial_plat *plat = dev_get_plat(dev);
301 struct pl01x_priv *priv = dev_get_priv(dev);
302
303 if (!plat->skip_init) {
304 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
305 baudrate);
306 }
307
308 return 0;
309 }
310
pl01x_serial_probe(struct udevice * dev)311 int pl01x_serial_probe(struct udevice *dev)
312 {
313 struct pl01x_serial_plat *plat = dev_get_plat(dev);
314 struct pl01x_priv *priv = dev_get_priv(dev);
315 int ret;
316
317 #if CONFIG_IS_ENABLED(OF_PLATDATA)
318 struct dtd_serial_pl01x *dtplat = &plat->dtplat;
319
320 priv->regs = (struct pl01x_regs *)dtplat->reg[0];
321 plat->type = dtplat->type;
322 #else
323 priv->regs = (struct pl01x_regs *)plat->base;
324 #endif
325 priv->type = plat->type;
326
327 if (!plat->skip_init) {
328 ret = pl01x_generic_serial_init(priv->regs, priv->type);
329 if (ret)
330 return ret;
331 return pl01x_serial_setbrg(dev, gd->baudrate);
332 } else {
333 return 0;
334 }
335 }
336
pl01x_serial_getc(struct udevice * dev)337 int pl01x_serial_getc(struct udevice *dev)
338 {
339 struct pl01x_priv *priv = dev_get_priv(dev);
340
341 return pl01x_getc(priv->regs);
342 }
343
pl01x_serial_putc(struct udevice * dev,const char ch)344 int pl01x_serial_putc(struct udevice *dev, const char ch)
345 {
346 struct pl01x_priv *priv = dev_get_priv(dev);
347
348 return pl01x_putc(priv->regs, ch);
349 }
350
pl01x_serial_pending(struct udevice * dev,bool input)351 int pl01x_serial_pending(struct udevice *dev, bool input)
352 {
353 struct pl01x_priv *priv = dev_get_priv(dev);
354 unsigned int fr = readl(&priv->regs->fr);
355
356 if (input)
357 return pl01x_tstc(priv->regs);
358 else
359 return fr & UART_PL01x_FR_TXFE ? 0 : 1;
360 }
361
362 static const struct dm_serial_ops pl01x_serial_ops = {
363 .putc = pl01x_serial_putc,
364 .pending = pl01x_serial_pending,
365 .getc = pl01x_serial_getc,
366 .setbrg = pl01x_serial_setbrg,
367 .getinfo = pl01x_serial_getinfo,
368 };
369
370 #if CONFIG_IS_ENABLED(OF_REAL)
371 static const struct udevice_id pl01x_serial_id[] ={
372 {.compatible = "arm,pl011", .data = TYPE_PL011},
373 {.compatible = "arm,pl010", .data = TYPE_PL010},
374 {}
375 };
376
377 #ifndef CFG_PL011_CLOCK
378 #define CFG_PL011_CLOCK 0
379 #endif
380
pl01x_serial_of_to_plat(struct udevice * dev)381 int pl01x_serial_of_to_plat(struct udevice *dev)
382 {
383 struct pl01x_serial_plat *plat = dev_get_plat(dev);
384 struct clk clk;
385 fdt_addr_t addr;
386 int ret;
387
388 addr = dev_read_addr(dev);
389 if (addr == FDT_ADDR_T_NONE)
390 return -EINVAL;
391
392 plat->base = addr;
393 plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK);
394 ret = clk_get_by_index(dev, 0, &clk);
395 if (!ret) {
396 ret = clk_enable(&clk);
397 if (ret && ret != -ENOSYS) {
398 dev_err(dev, "failed to enable clock\n");
399 return ret;
400 }
401
402 plat->clock = clk_get_rate(&clk);
403 if (IS_ERR_VALUE(plat->clock)) {
404 dev_err(dev, "failed to get rate\n");
405 return plat->clock;
406 }
407 debug("%s: CLK %d\n", __func__, plat->clock);
408 }
409 plat->type = dev_get_driver_data(dev);
410 plat->skip_init = dev_read_bool(dev, "skip-init");
411
412 return 0;
413 }
414 #endif
415
416 U_BOOT_DRIVER(serial_pl01x) = {
417 .name = "serial_pl01x",
418 .id = UCLASS_SERIAL,
419 #if CONFIG_IS_ENABLED(OF_REAL)
420 .of_match = of_match_ptr(pl01x_serial_id),
421 .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
422 #endif
423 .plat_auto = sizeof(struct pl01x_serial_plat),
424 .probe = pl01x_serial_probe,
425 .ops = &pl01x_serial_ops,
426 .flags = DM_FLAG_PRE_RELOC,
427 .priv_auto = sizeof(struct pl01x_priv),
428 };
429
DM_DRIVER_ALIAS(serial_pl01x,arm_pl011)430 DM_DRIVER_ALIAS(serial_pl01x, arm_pl011)
431 DM_DRIVER_ALIAS(serial_pl01x, arm_pl010)
432 #endif
433
434 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
435
436 #include <debug_uart.h>
437
438 static void _debug_uart_init(void)
439 {
440 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
441 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
442 enum pl01x_type type;
443
444 if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
445 type = TYPE_PL011;
446 else
447 type = TYPE_PL010;
448
449 pl01x_generic_serial_init(regs, type);
450 pl01x_generic_setbrg(regs, type,
451 CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
452 #endif
453 }
454
_debug_uart_putc(int ch)455 static inline void _debug_uart_putc(int ch)
456 {
457 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
458
459 while (pl01x_putc(regs, ch) == -EAGAIN)
460 ;
461 }
462
463 DEBUG_UART_FUNCS
464
465 #endif
466