1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 SAMSUNG Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Heungjun Kim <riverful.kim@samsung.com>
6 *
7 * based on drivers/serial/s3c64xx.c
8 */
9
10 #include <dm.h>
11 #include <errno.h>
12 #include <fdtdec.h>
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15 #include <asm/io.h>
16 #if !IS_ENABLED(CONFIG_ARCH_APPLE)
17 #include <asm/arch/clk.h>
18 #endif
19 #include <asm/arch/uart.h>
20 #include <serial.h>
21 #include <clk.h>
22
23 enum {
24 PORT_S5P = 0,
25 PORT_S5L
26 };
27
28 #define UFCON_FIFO_EN BIT(0)
29 #define UFCON_RX_FIFO_RESET BIT(1)
30 #define UMCON_RESET_VAL 0x0
31 #define ULCON_WORD_8_BIT 0x3
32 #define UCON_RX_IRQ_OR_POLLING BIT(0)
33 #define UCON_TX_IRQ_OR_POLLING BIT(2)
34 #define UCON_RX_ERR_IRQ_EN BIT(6)
35 #define UCON_TX_IRQ_LEVEL BIT(9)
36
37 #define S5L_RX_FIFO_COUNT_SHIFT 0
38 #define S5L_RX_FIFO_COUNT_MASK (0xf << S5L_RX_FIFO_COUNT_SHIFT)
39 #define S5L_RX_FIFO_FULL BIT(8)
40 #define S5L_TX_FIFO_COUNT_SHIFT 4
41 #define S5L_TX_FIFO_COUNT_MASK (0xf << S5L_TX_FIFO_COUNT_SHIFT)
42 #define S5L_TX_FIFO_FULL BIT(9)
43
44 #define S5P_RX_FIFO_COUNT_SHIFT 0
45 #define S5P_RX_FIFO_COUNT_MASK (0xff << S5P_RX_FIFO_COUNT_SHIFT)
46 #define S5P_RX_FIFO_FULL BIT(8)
47 #define S5P_TX_FIFO_COUNT_SHIFT 16
48 #define S5P_TX_FIFO_COUNT_MASK (0xff << S5P_TX_FIFO_COUNT_SHIFT)
49 #define S5P_TX_FIFO_FULL BIT(24)
50
51 /* Information about a serial port */
52 struct s5p_serial_plat {
53 struct s5p_uart *reg; /* address of registers in physical memory */
54 u8 reg_width; /* register width */
55 u8 port_id; /* uart port number */
56 u8 rx_fifo_count_shift;
57 u8 tx_fifo_count_shift;
58 u32 rx_fifo_count_mask;
59 u32 tx_fifo_count_mask;
60 u32 rx_fifo_full;
61 u32 tx_fifo_full;
62 };
63
64 /*
65 * The coefficient, used to calculate the baudrate on S5P UARTs is
66 * calculated as
67 * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
68 * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
69 * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
70 */
71 static const int udivslot[] = {
72 0,
73 0x0080,
74 0x0808,
75 0x0888,
76 0x2222,
77 0x4924,
78 0x4a52,
79 0x54aa,
80 0x5555,
81 0xd555,
82 0xd5d5,
83 0xddd5,
84 0xdddd,
85 0xdfdd,
86 0xdfdf,
87 0xffdf,
88 };
89
s5p_serial_init(struct s5p_uart * uart)90 static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
91 {
92 /* Enable FIFOs, auto clear Rx FIFO */
93 writel(UFCON_FIFO_EN | UFCON_RX_FIFO_RESET, &uart->ufcon);
94 /* No auto flow control, disable nRTS signal */
95 writel(UMCON_RESET_VAL, &uart->umcon);
96 /* 8N1, no parity bit */
97 writel(ULCON_WORD_8_BIT, &uart->ulcon);
98 /* No interrupts, no DMA, pure polling */
99 writel(UCON_RX_IRQ_OR_POLLING | UCON_TX_IRQ_OR_POLLING |
100 UCON_RX_ERR_IRQ_EN | UCON_TX_IRQ_LEVEL, &uart->ucon);
101 }
102
s5p_serial_baud(struct s5p_uart * uart,u8 reg_width,uint uclk,int baudrate)103 static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
104 uint uclk, int baudrate)
105 {
106 u32 val;
107
108 val = uclk / baudrate;
109
110 writel(val / 16 - 1, &uart->ubrdiv);
111
112 if (s5p_uart_divslot())
113 writew(udivslot[val % 16], &uart->rest.slot);
114 else if (reg_width == 4)
115 writel(val % 16, &uart->rest.value);
116 else
117 writeb(val % 16, &uart->rest.value);
118 }
119
120 #ifndef CONFIG_XPL_BUILD
s5p_serial_setbrg(struct udevice * dev,int baudrate)121 int s5p_serial_setbrg(struct udevice *dev, int baudrate)
122 {
123 struct s5p_serial_plat *plat = dev_get_plat(dev);
124 struct s5p_uart *const uart = plat->reg;
125 u32 uclk;
126
127 #if IS_ENABLED(CONFIG_CLK_EXYNOS) || IS_ENABLED(CONFIG_ARCH_APPLE)
128 struct clk clk;
129 int ret;
130
131 ret = clk_get_by_index(dev, 1, &clk);
132 if (ret < 0)
133 return ret;
134 uclk = clk_get_rate(&clk);
135 #else
136 uclk = get_uart_clk(plat->port_id);
137 #endif
138
139 s5p_serial_baud(uart, plat->reg_width, uclk, baudrate);
140
141 return 0;
142 }
143
s5p_serial_probe(struct udevice * dev)144 static int s5p_serial_probe(struct udevice *dev)
145 {
146 struct s5p_serial_plat *plat = dev_get_plat(dev);
147 struct s5p_uart *const uart = plat->reg;
148
149 s5p_serial_init(uart);
150
151 return 0;
152 }
153
serial_err_check(const struct s5p_uart * const uart,int op)154 static int serial_err_check(const struct s5p_uart *const uart, int op)
155 {
156 unsigned int mask;
157
158 /*
159 * UERSTAT
160 * Break Detect [3]
161 * Frame Err [2] : receive operation
162 * Parity Err [1] : receive operation
163 * Overrun Err [0] : receive operation
164 */
165 if (op)
166 mask = 0x8;
167 else
168 mask = 0xf;
169
170 return readl(&uart->uerstat) & mask;
171 }
172
s5p_serial_getc(struct udevice * dev)173 static int s5p_serial_getc(struct udevice *dev)
174 {
175 struct s5p_serial_plat *plat = dev_get_plat(dev);
176 struct s5p_uart *const uart = plat->reg;
177
178 if (!(readl(&uart->ufstat) & plat->rx_fifo_count_mask))
179 return -EAGAIN;
180
181 serial_err_check(uart, 0);
182 if (plat->reg_width == 4)
183 return (int)(readl(&uart->urxh) & 0xff);
184 else
185 return (int)(readb(&uart->urxh) & 0xff);
186 }
187
s5p_serial_putc(struct udevice * dev,const char ch)188 static int s5p_serial_putc(struct udevice *dev, const char ch)
189 {
190 struct s5p_serial_plat *plat = dev_get_plat(dev);
191 struct s5p_uart *const uart = plat->reg;
192
193 if (readl(&uart->ufstat) & plat->tx_fifo_full)
194 return -EAGAIN;
195
196 if (plat->reg_width == 4)
197 writel(ch, &uart->utxh);
198 else
199 writeb(ch, &uart->utxh);
200 serial_err_check(uart, 1);
201
202 return 0;
203 }
204
s5p_serial_pending(struct udevice * dev,bool input)205 static int s5p_serial_pending(struct udevice *dev, bool input)
206 {
207 struct s5p_serial_plat *plat = dev_get_plat(dev);
208 struct s5p_uart *const uart = plat->reg;
209 uint32_t ufstat = readl(&uart->ufstat);
210
211 if (input) {
212 return (ufstat & plat->rx_fifo_count_mask) >>
213 plat->rx_fifo_count_shift;
214 } else {
215 return (ufstat & plat->tx_fifo_count_mask) >>
216 plat->tx_fifo_count_shift;
217 }
218 }
219
s5p_serial_of_to_plat(struct udevice * dev)220 static int s5p_serial_of_to_plat(struct udevice *dev)
221 {
222 struct s5p_serial_plat *plat = dev_get_plat(dev);
223 const ulong port_type = dev_get_driver_data(dev);
224
225 plat->reg = dev_read_addr_ptr(dev);
226 if (!plat->reg)
227 return -EINVAL;
228
229 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
230 plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
231
232 if (port_type == PORT_S5L) {
233 plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
234 plat->rx_fifo_count_mask = S5L_RX_FIFO_COUNT_MASK;
235 plat->rx_fifo_full = S5L_RX_FIFO_FULL;
236 plat->tx_fifo_count_shift = S5L_TX_FIFO_COUNT_SHIFT;
237 plat->tx_fifo_count_mask = S5L_TX_FIFO_COUNT_MASK;
238 plat->tx_fifo_full = S5L_TX_FIFO_FULL;
239 } else {
240 plat->rx_fifo_count_shift = S5P_RX_FIFO_COUNT_SHIFT;
241 plat->rx_fifo_count_mask = S5P_RX_FIFO_COUNT_MASK;
242 plat->rx_fifo_full = S5P_RX_FIFO_FULL;
243 plat->tx_fifo_count_shift = S5P_TX_FIFO_COUNT_SHIFT;
244 plat->tx_fifo_count_mask = S5P_TX_FIFO_COUNT_MASK;
245 plat->tx_fifo_full = S5P_TX_FIFO_FULL;
246 }
247
248 return 0;
249 }
250
251 static const struct dm_serial_ops s5p_serial_ops = {
252 .putc = s5p_serial_putc,
253 .pending = s5p_serial_pending,
254 .getc = s5p_serial_getc,
255 .setbrg = s5p_serial_setbrg,
256 };
257
258 static const struct udevice_id s5p_serial_ids[] = {
259 { .compatible = "samsung,exynos4210-uart", .data = PORT_S5P },
260 { .compatible = "samsung,exynos850-uart", .data = PORT_S5P },
261 { .compatible = "apple,s5l-uart", .data = PORT_S5L },
262 { }
263 };
264
265 U_BOOT_DRIVER(serial_s5p) = {
266 .name = "serial_s5p",
267 .id = UCLASS_SERIAL,
268 .of_match = s5p_serial_ids,
269 .of_to_plat = s5p_serial_of_to_plat,
270 .plat_auto = sizeof(struct s5p_serial_plat),
271 .probe = s5p_serial_probe,
272 .ops = &s5p_serial_ops,
273 };
274 #endif
275
276 #ifdef CONFIG_DEBUG_UART_S5P
277
278 #include <debug_uart.h>
279
_debug_uart_init(void)280 static inline void _debug_uart_init(void)
281 {
282 if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
283 return;
284
285 struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
286
287 s5p_serial_init(uart);
288 #if IS_ENABLED(CONFIG_ARCH_APPLE)
289 s5p_serial_baud(uart, 4, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
290 #else
291 s5p_serial_baud(uart, 1, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
292 #endif
293 }
294
_debug_uart_putc(int ch)295 static inline void _debug_uart_putc(int ch)
296 {
297 struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
298
299 #if IS_ENABLED(CONFIG_ARCH_APPLE)
300 while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL)
301 ;
302 writel(ch, &uart->utxh);
303 #else
304 while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL)
305 ;
306 writeb(ch, &uart->utxh);
307 #endif
308 }
309
310 DEBUG_UART_FUNCS
311
312 #endif
313