1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_SERIAL
8
9 #include <clk.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <reset.h>
13 #include <serial.h>
14 #include <watchdog.h>
15 #include <asm/io.h>
16 #include <asm/arch/stm32.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/iopoll.h>
21 #include "serial_stm32.h"
22 #include <dm/device_compat.h>
23
24 /*
25 * At 115200 bits/s
26 * 1 bit = 1 / 115200 = 8,68 us
27 * 8 bits = 69,444 us
28 * 10 bits are needed for worst case (8 bits + 1 start + 1 stop) = 86.806 us
29 */
30 #define ONE_BYTE_B115200_US 87
31
_stm32_serial_setbrg(void __iomem * base,struct stm32_uart_info * uart_info,u32 clock_rate,int baudrate)32 static void _stm32_serial_setbrg(void __iomem *base,
33 struct stm32_uart_info *uart_info,
34 u32 clock_rate,
35 int baudrate)
36 {
37 bool stm32f4 = uart_info->stm32f4;
38 u32 int_div, mantissa, fraction, oversampling;
39 u8 uart_enable_bit = uart_info->uart_enable_bit;
40
41 /* BRR register must be set when uart is disabled */
42 clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
43
44 int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
45
46 if (int_div < 16) {
47 oversampling = 8;
48 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
49 } else {
50 oversampling = 16;
51 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
52 }
53
54 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
55 fraction = int_div % oversampling;
56
57 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
58
59 setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit));
60 }
61
stm32_serial_setbrg(struct udevice * dev,int baudrate)62 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
63 {
64 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
65
66 _stm32_serial_setbrg(plat->base, plat->uart_info,
67 plat->clock_rate, baudrate);
68
69 return 0;
70 }
71
stm32_serial_setconfig(struct udevice * dev,uint serial_config)72 static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
73 {
74 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
75 bool stm32f4 = plat->uart_info->stm32f4;
76 u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
77 void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4);
78 u32 config = 0;
79 uint parity = SERIAL_GET_PARITY(serial_config);
80 uint bits = SERIAL_GET_BITS(serial_config);
81 uint stop = SERIAL_GET_STOP(serial_config);
82
83 /*
84 * only parity config is implemented, check if other serial settings
85 * are the default one.
86 * (STM32F4 serial IP didn't support parity setting)
87 */
88 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
89 return -ENOTSUPP; /* not supported in driver*/
90
91 clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
92 /* update usart configuration (uart need to be disable)
93 * PCE: parity check enable
94 * PS : '0' : Even / '1' : Odd
95 * M[1:0] = '00' : 8 Data bits
96 * M[1:0] = '01' : 9 Data bits with parity
97 */
98 switch (parity) {
99 default:
100 case SERIAL_PAR_NONE:
101 config = 0;
102 break;
103 case SERIAL_PAR_ODD:
104 config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
105 break;
106 case SERIAL_PAR_EVEN:
107 config = USART_CR1_PCE | USART_CR1_M0;
108 break;
109 }
110
111 clrsetbits_le32(cr1,
112 USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
113 USART_CR1_M0,
114 config);
115 setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
116
117 return 0;
118 }
119
stm32_serial_getc(struct udevice * dev)120 static int stm32_serial_getc(struct udevice *dev)
121 {
122 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
123 bool stm32f4 = plat->uart_info->stm32f4;
124 void __iomem *base = plat->base;
125 u32 isr = readl(base + ISR_OFFSET(stm32f4));
126
127 if ((isr & USART_ISR_RXNE) == 0)
128 return -EAGAIN;
129
130 if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
131 if (!stm32f4)
132 setbits_le32(base + ICR_OFFSET,
133 USART_ICR_PCECF | USART_ICR_ORECF |
134 USART_ICR_FECF);
135 else
136 readl(base + RDR_OFFSET(stm32f4));
137 return -EIO;
138 }
139
140 return readl(base + RDR_OFFSET(stm32f4));
141 }
142
_stm32_serial_putc(void __iomem * base,struct stm32_uart_info * uart_info,const char c)143 static int _stm32_serial_putc(void __iomem *base,
144 struct stm32_uart_info *uart_info,
145 const char c)
146 {
147 bool stm32f4 = uart_info->stm32f4;
148
149 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
150 return -EAGAIN;
151
152 writel(c, base + TDR_OFFSET(stm32f4));
153
154 return 0;
155 }
156
stm32_serial_putc(struct udevice * dev,const char c)157 static int stm32_serial_putc(struct udevice *dev, const char c)
158 {
159 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
160
161 return _stm32_serial_putc(plat->base, plat->uart_info, c);
162 }
163
stm32_serial_pending(struct udevice * dev,bool input)164 static int stm32_serial_pending(struct udevice *dev, bool input)
165 {
166 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
167 bool stm32f4 = plat->uart_info->stm32f4;
168 void __iomem *base = plat->base;
169
170 if (input)
171 return readl(base + ISR_OFFSET(stm32f4)) &
172 USART_ISR_RXNE ? 1 : 0;
173 else
174 return readl(base + ISR_OFFSET(stm32f4)) &
175 USART_ISR_TXE ? 0 : 1;
176 }
177
_stm32_serial_init(void __iomem * base,struct stm32_uart_info * uart_info)178 static void _stm32_serial_init(void __iomem *base,
179 struct stm32_uart_info *uart_info)
180 {
181 bool stm32f4 = uart_info->stm32f4;
182 u8 uart_enable_bit = uart_info->uart_enable_bit;
183
184 /* Disable uart-> enable fifo -> enable uart */
185 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
186 BIT(uart_enable_bit));
187 if (uart_info->has_fifo)
188 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
189 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
190 BIT(uart_enable_bit));
191 }
192
stm32_serial_probe(struct udevice * dev)193 static int stm32_serial_probe(struct udevice *dev)
194 {
195 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
196 struct clk clk;
197 struct reset_ctl reset;
198 u32 isr;
199 int ret;
200 bool stm32f4;
201
202 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
203 stm32f4 = plat->uart_info->stm32f4;
204
205 ret = clk_get_by_index(dev, 0, &clk);
206 if (ret < 0)
207 return ret;
208
209 ret = clk_enable(&clk);
210 if (ret) {
211 dev_err(dev, "failed to enable clock\n");
212 return ret;
213 }
214
215 /*
216 * before uart initialization, wait for TC bit (Transmission Complete)
217 * in case there is still chars from previous bootstage to transmit
218 */
219 ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 50,
220 16 * ONE_BYTE_B115200_US, plat->base + ISR_OFFSET(stm32f4));
221 if (ret)
222 dev_dbg(dev, "FIFO not empty, some character can be lost (%d)\n", ret);
223
224 ret = reset_get_by_index(dev, 0, &reset);
225 if (!ret) {
226 reset_assert(&reset);
227 udelay(2);
228 reset_deassert(&reset);
229 }
230
231 plat->clock_rate = clk_get_rate(&clk);
232 if (!plat->clock_rate) {
233 clk_disable(&clk);
234 return -EINVAL;
235 };
236
237 _stm32_serial_init(plat->base, plat->uart_info);
238
239 return 0;
240 }
241
242 static const struct udevice_id stm32_serial_id[] = {
243 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
244 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
245 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
246 {}
247 };
248
stm32_serial_of_to_plat(struct udevice * dev)249 static int stm32_serial_of_to_plat(struct udevice *dev)
250 {
251 struct stm32x7_serial_plat *plat = dev_get_plat(dev);
252 fdt_addr_t addr;
253
254 addr = dev_read_addr(dev);
255 if (addr == FDT_ADDR_T_NONE)
256 return -EINVAL;
257
258 plat->base = (void __iomem *)addr;
259
260 return 0;
261 }
262
263 static const struct dm_serial_ops stm32_serial_ops = {
264 .putc = stm32_serial_putc,
265 .pending = stm32_serial_pending,
266 .getc = stm32_serial_getc,
267 .setbrg = stm32_serial_setbrg,
268 .setconfig = stm32_serial_setconfig
269 };
270
271 U_BOOT_DRIVER(serial_stm32) = {
272 .name = "serial_stm32",
273 .id = UCLASS_SERIAL,
274 .of_match = of_match_ptr(stm32_serial_id),
275 .of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
276 .plat_auto = sizeof(struct stm32x7_serial_plat),
277 .ops = &stm32_serial_ops,
278 .probe = stm32_serial_probe,
279 #if !CONFIG_IS_ENABLED(OF_CONTROL)
280 .flags = DM_FLAG_PRE_RELOC,
281 #endif
282 };
283
284 #ifdef CONFIG_DEBUG_UART_STM32
285 #include <debug_uart.h>
_debug_uart_info(void)286 static inline struct stm32_uart_info *_debug_uart_info(void)
287 {
288 struct stm32_uart_info *uart_info;
289
290 #if defined(CONFIG_STM32F4)
291 uart_info = &stm32f4_info;
292 #elif defined(CONFIG_STM32F7)
293 uart_info = &stm32f7_info;
294 #else
295 uart_info = &stm32h7_info;
296 #endif
297 return uart_info;
298 }
299
_debug_uart_init(void)300 static inline void _debug_uart_init(void)
301 {
302 void __maybe_unused __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
303 struct stm32_uart_info *uart_info __maybe_unused = _debug_uart_info();
304
305 /*
306 * debug_uart_init() is only usable when SPL_BUILD is enabled
307 * (STM32MP1 case only)
308 */
309 if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) {
310 _stm32_serial_init(base, uart_info);
311 _stm32_serial_setbrg(base, uart_info,
312 CONFIG_DEBUG_UART_CLOCK,
313 CONFIG_BAUDRATE);
314 }
315 }
316
_debug_uart_putc(int c)317 static inline void _debug_uart_putc(int c)
318 {
319 void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
320 struct stm32_uart_info *uart_info = _debug_uart_info();
321
322 while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
323 ;
324 }
325
326 DEBUG_UART_FUNCS
327 #endif
328