1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator
4 * Manager (RA) subsystem driver
5 *
6 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
7 */
8
9 struct k3_nav_ring_cfg_regs {
10 u32 resv_64[16];
11 u32 ba_lo; /* Ring Base Address Lo Register */
12 u32 ba_hi; /* Ring Base Address Hi Register */
13 u32 size; /* Ring Size Register */
14 u32 event; /* Ring Event Register */
15 u32 orderid; /* Ring OrderID Register */
16 };
17
18 #define KNAV_RINGACC_CFG_REGS_STEP 0x100
19
20 #define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0)
21
22 #define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30)
23 #define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30)
24
25 #define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24)
26 #define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24)
27
28 #define KNAV_RINGACC_CFG_RING_SIZE_MASK GENMASK(19, 0)
29
k3_ringacc_ring_reset_raw(struct k3_nav_ring * ring)30 static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
31 {
32 u32 reg;
33
34 reg = readl(&ring->cfg->size);
35 reg &= ~KNAV_RINGACC_CFG_RING_SIZE_MASK;
36 reg |= ring->size;
37 writel(reg, &ring->cfg->size);
38 }
39
k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring * ring,enum k3_nav_ring_mode mode)40 static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode)
41 {
42 u32 val;
43
44 val = readl(&ring->cfg->size);
45 val &= ~KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
46 val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
47 writel(val, &ring->cfg->size);
48 }
49
k3_ringacc_ring_free_raw(struct k3_nav_ring * ring)50 static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring)
51 {
52 writel(0, &ring->cfg->ba_hi);
53 writel(0, &ring->cfg->ba_lo);
54 writel(0, &ring->cfg->size);
55 }
56
k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring * ring)57 static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring)
58 {
59 u32 val;
60
61 writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
62 writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
63
64 val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT |
65 ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT |
66 ring->size;
67 writel(val, &ring->cfg->size);
68 }
69