1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 *
5 * Copyright 2011 Maxim Integrated Products
6 */
7
8 #include <audio_codec.h>
9 #include <div64.h>
10 #include <dm.h>
11 #include <i2c.h>
12 #include <i2s.h>
13 #include <log.h>
14 #include <sound.h>
15 #include <asm/gpio.h>
16 #include <linux/delay.h>
17 #include "maxim_codec.h"
18 #include "max98090.h"
19
20 /*
21 * Sets hw params for max98090
22 *
23 * @priv: max98090 information pointer
24 * @rate: Sampling rate
25 * @bits_per_sample: Bits per sample
26 *
27 * Return: -EIO for error, 0 for success.
28 */
max98090_hw_params(struct maxim_priv * priv,unsigned int rate,unsigned int bits_per_sample)29 int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
30 unsigned int bits_per_sample)
31 {
32 int error;
33 unsigned char value;
34
35 switch (bits_per_sample) {
36 case 16:
37 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
38 error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
39 M98090_WS_MASK, 0);
40 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
41 break;
42 default:
43 debug("%s: Illegal bits per sample %d.\n",
44 __func__, bits_per_sample);
45 return -1;
46 }
47
48 /* Update filter mode */
49 if (rate < 240000)
50 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
51 M98090_MODE_MASK, 0);
52 else
53 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
54 M98090_MODE_MASK, M98090_MODE_MASK);
55
56 /* Update sample rate mode */
57 if (rate < 50000)
58 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
59 M98090_DHF_MASK, 0);
60 else
61 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
62 M98090_DHF_MASK, M98090_DHF_MASK);
63
64 if (error < 0) {
65 debug("%s: Error setting hardware params.\n", __func__);
66 return -EIO;
67 }
68 priv->rate = rate;
69
70 return 0;
71 }
72
73 /*
74 * Configures Audio interface system clock for the given frequency
75 *
76 * @priv: max98090 information
77 * @freq: Sampling frequency in Hz
78 *
79 * Return: -EIO for error, 0 for success.
80 */
max98090_set_sysclk(struct maxim_priv * priv,unsigned int freq)81 int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
82 {
83 int error = 0;
84
85 /* Requested clock frequency is already setup */
86 if (freq == priv->sysclk)
87 return 0;
88
89 /* Setup clocks for slave mode, and using the PLL
90 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
91 * 0x02 (when master clk is 20MHz to 40MHz)..
92 * 0x03 (when master clk is 40MHz to 60MHz)..
93 */
94 if (freq >= 10000000 && freq < 20000000) {
95 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
96 M98090_PSCLK_DIV1);
97 } else if (freq >= 20000000 && freq < 40000000) {
98 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
99 M98090_PSCLK_DIV2);
100 } else if (freq >= 40000000 && freq < 60000000) {
101 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
102 M98090_PSCLK_DIV4);
103 } else {
104 debug("%s: Invalid master clock frequency\n", __func__);
105 return -1;
106 }
107
108 debug("%s: Clock at %uHz\n", __func__, freq);
109
110 if (error < 0)
111 return -1;
112
113 priv->sysclk = freq;
114
115 return 0;
116 }
117
118 /*
119 * Sets Max98090 I2S format
120 *
121 * @priv: max98090 information
122 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
123 *
124 * Return: -EIO for error, 0 for success.
125 */
max98090_set_fmt(struct maxim_priv * priv,int fmt)126 int max98090_set_fmt(struct maxim_priv *priv, int fmt)
127 {
128 u8 regval = 0;
129 int error = 0;
130
131 if (fmt == priv->fmt)
132 return 0;
133
134 priv->fmt = fmt;
135
136 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
137 case SND_SOC_DAIFMT_CBS_CFS:
138 /* Set to slave mode PLL - MAS mode off */
139 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
140 0x00);
141 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
142 0x00);
143 error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
144 M98090_USE_M1_MASK, 0);
145 break;
146 case SND_SOC_DAIFMT_CBM_CFM:
147 /* Set to master mode */
148 debug("Master mode not supported\n");
149 break;
150 case SND_SOC_DAIFMT_CBS_CFM:
151 case SND_SOC_DAIFMT_CBM_CFS:
152 default:
153 debug("%s: Clock mode unsupported\n", __func__);
154 return -EINVAL;
155 }
156
157 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
158
159 regval = 0;
160 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
161 case SND_SOC_DAIFMT_I2S:
162 regval |= M98090_DLY_MASK;
163 break;
164 case SND_SOC_DAIFMT_LEFT_J:
165 break;
166 case SND_SOC_DAIFMT_RIGHT_J:
167 regval |= M98090_RJ_MASK;
168 break;
169 case SND_SOC_DAIFMT_DSP_A:
170 /* Not supported mode */
171 default:
172 debug("%s: Unrecognized format.\n", __func__);
173 return -EINVAL;
174 }
175
176 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
177 case SND_SOC_DAIFMT_NB_NF:
178 break;
179 case SND_SOC_DAIFMT_NB_IF:
180 regval |= M98090_WCI_MASK;
181 break;
182 case SND_SOC_DAIFMT_IB_NF:
183 regval |= M98090_BCI_MASK;
184 break;
185 case SND_SOC_DAIFMT_IB_IF:
186 regval |= M98090_BCI_MASK | M98090_WCI_MASK;
187 break;
188 default:
189 debug("%s: Unrecognized inversion settings.\n", __func__);
190 return -EINVAL;
191 }
192
193 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
194
195 if (error < 0) {
196 debug("%s: Error setting i2s format.\n", __func__);
197 return -EIO;
198 }
199
200 return 0;
201 }
202
203 /*
204 * resets the audio codec
205 *
206 * @priv: max98090 information
207 * Return: -EIO for error, 0 for success.
208 */
max98090_reset(struct maxim_priv * priv)209 static int max98090_reset(struct maxim_priv *priv)
210 {
211 int ret;
212
213 /*
214 * Gracefully reset the DSP core and the codec hardware in a proper
215 * sequence.
216 */
217 ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
218 M98090_SWRESET_MASK);
219 if (ret != 0) {
220 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
221 return ret;
222 }
223 mdelay(20);
224
225 return 0;
226 }
227
228 /*
229 * Initialise max98090 codec device
230 *
231 * @priv: max98090 information
232 *
233 * Return: -EIO for error, 0 for success.
234 */
max98090_device_init(struct maxim_priv * priv)235 int max98090_device_init(struct maxim_priv *priv)
236 {
237 unsigned char id;
238 int error = 0;
239
240 /* reset the codec, the DSP core, and disable all interrupts */
241 error = max98090_reset(priv);
242 if (error != 0) {
243 debug("Reset\n");
244 return error;
245 }
246
247 /* initialize private data */
248 priv->sysclk = -1U;
249 priv->rate = -1U;
250 priv->fmt = -1U;
251
252 error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
253 if (error < 0) {
254 debug("%s: Failure reading hardware revision: %d\n",
255 __func__, id);
256 return -EIO;
257 }
258 debug("%s: Hardware revision: %d\n", __func__, id);
259
260 return 0;
261 }
262
max98090_setup_interface(struct maxim_priv * priv)263 static int max98090_setup_interface(struct maxim_priv *priv)
264 {
265 unsigned char id;
266 int error;
267
268 /* Reading interrupt status to clear them */
269 error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
270
271 error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
272 M98090_DACHP_MASK);
273 error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
274 M98090_VCM_MODE_MASK);
275
276 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
277 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
278
279 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
280 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
281
282 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
283 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
284 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
285 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
286 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
287 M98090_SDIEN_MASK);
288 error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
289 M98090_SHDNN_MASK);
290 error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
291 M98090_HPREN_MASK | M98090_HPLEN_MASK |
292 M98090_SPREN_MASK | M98090_SPLEN_MASK |
293 M98090_DAREN_MASK | M98090_DALEN_MASK);
294 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
295 M98090_SDOEN_MASK | M98090_SDIEN_MASK);
296
297 if (error < 0)
298 return -EIO;
299
300 return 0;
301 }
302
max98090_do_init(struct maxim_priv * priv,int sampling_rate,int mclk_freq,int bits_per_sample)303 static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
304 int mclk_freq, int bits_per_sample)
305 {
306 int ret = 0;
307
308 ret = max98090_setup_interface(priv);
309 if (ret < 0) {
310 debug("%s: max98090 setup interface failed\n", __func__);
311 return ret;
312 }
313
314 ret = max98090_set_sysclk(priv, mclk_freq);
315 if (ret < 0) {
316 debug("%s: max98090 codec set sys clock failed\n", __func__);
317 return ret;
318 }
319
320 ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
321
322 if (ret == 0) {
323 ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
324 SND_SOC_DAIFMT_NB_NF |
325 SND_SOC_DAIFMT_CBS_CFS);
326 }
327
328 return ret;
329 }
330
max98090_set_params(struct udevice * dev,int interface,int rate,int mclk_freq,int bits_per_sample,uint channels)331 static int max98090_set_params(struct udevice *dev, int interface, int rate,
332 int mclk_freq, int bits_per_sample,
333 uint channels)
334 {
335 struct maxim_priv *priv = dev_get_priv(dev);
336
337 return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
338 }
339
max98090_probe(struct udevice * dev)340 static int max98090_probe(struct udevice *dev)
341 {
342 struct maxim_priv *priv = dev_get_priv(dev);
343 int ret;
344
345 priv->dev = dev;
346 ret = max98090_device_init(priv);
347 if (ret < 0) {
348 debug("%s: max98090 codec chip init failed\n", __func__);
349 return ret;
350 }
351
352 return 0;
353 }
354
355 static const struct audio_codec_ops max98090_ops = {
356 .set_params = max98090_set_params,
357 };
358
359 static const struct udevice_id max98090_ids[] = {
360 { .compatible = "maxim,max98090" },
361 { }
362 };
363
364 U_BOOT_DRIVER(max98090) = {
365 .name = "max98090",
366 .id = UCLASS_AUDIO_CODEC,
367 .of_match = max98090_ids,
368 .probe = max98090_probe,
369 .ops = &max98090_ops,
370 .priv_auto = sizeof(struct maxim_priv),
371 };
372