1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 *
10 * Support for DM and DT, non-DM code removed.
11 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
12 *
13 * TODO: fsl_dspi.c should work as a driver for the DSPI module.
14 */
15
16 #include <dm.h>
17 #include <log.h>
18 #include <asm/global_data.h>
19 #include <dm/platform_data/spi_coldfire.h>
20 #include <spi.h>
21 #include <malloc.h>
22 #include <asm/coldfire/dspi.h>
23 #include <asm/io.h>
24
25 struct coldfire_spi_priv {
26 struct dspi *regs;
27 uint baudrate;
28 int mode;
29 int charbit;
30 };
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #ifndef SPI_IDLE_VAL
35 #if defined(CONFIG_SPI_MMC)
36 #define SPI_IDLE_VAL 0xFFFF
37 #else
38 #define SPI_IDLE_VAL 0x0
39 #endif
40 #endif
41
42 /*
43 * DSPI specific mode
44 *
45 * bit 31 - 28: Transfer size 3 to 16 bits
46 * 27 - 26: PCS to SCK delay prescaler
47 * 25 - 24: After SCK delay prescaler
48 * 23 - 22: Delay after transfer prescaler
49 * 21 : Allow overwrite for bit 31-22 and bit 20-8
50 * 20 : Double baud rate
51 * 19 - 16: PCS to SCK delay scaler
52 * 15 - 12: After SCK delay scaler
53 * 11 - 8: Delay after transfer scaler
54 * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
55 */
56 #define SPI_MODE_MOD 0x00200000
57 #define SPI_MODE_DBLRATE 0x00100000
58
59 #define SPI_MODE_XFER_SZ_MASK 0xf0000000
60 #define SPI_MODE_DLY_PRE_MASK 0x0fc00000
61 #define SPI_MODE_DLY_SCA_MASK 0x000fff00
62
63 #define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
64 #define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
65 #define MCF_DSPI_MAX_CTAR_REGS 8
66
67 /* Default values */
68 #define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
69 #define MCF_DSPI_DEFAULT_MAX_CS 4
70 #define MCF_DSPI_DEFAULT_MODE 0
71
72 #define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
73 DSPI_CTAR_PCSSCK_1CLK | \
74 DSPI_CTAR_PASC(0) | \
75 DSPI_CTAR_PDT(0) | \
76 DSPI_CTAR_CSSCK(0) | \
77 DSPI_CTAR_ASC(0) | \
78 DSPI_CTAR_DT(1) | \
79 DSPI_CTAR_BR(6))
80
81 #define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
82 DSPI_CTAR_PCSSCK(3) | \
83 DSPI_CTAR_PASC_7CLK | \
84 DSPI_CTAR_PDT(3) | \
85 DSPI_CTAR_CSSCK(0x0f) | \
86 DSPI_CTAR_ASC(0x0f) | \
87 DSPI_CTAR_DT(0x0f))
88
89 #define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
90
cfspi_tx(struct coldfire_spi_priv * cfspi,u32 ctrl,u16 data)91 static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
92 u32 ctrl, u16 data)
93 {
94 /*
95 * Need to check fifo level here
96 */
97 while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
98 ;
99
100 writel(ctrl | data, &cfspi->regs->tfr);
101 }
102
cfspi_rx(struct coldfire_spi_priv * cfspi)103 static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
104 {
105
106 while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
107 ;
108
109 return readw(&cfspi->regs->rfr);
110 }
111
coldfire_spi_claim_bus(struct udevice * dev)112 static int coldfire_spi_claim_bus(struct udevice *dev)
113 {
114 struct udevice *bus = dev->parent;
115 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
116 struct dspi *dspi = cfspi->regs;
117 struct dm_spi_slave_plat *slave_plat =
118 dev_get_parent_plat(dev);
119
120 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
121 return -1;
122
123 /* Clear FIFO and resume transfer */
124 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
125
126 dspi_chip_select(slave_plat->cs[0]);
127
128 return 0;
129 }
130
coldfire_spi_release_bus(struct udevice * dev)131 static int coldfire_spi_release_bus(struct udevice *dev)
132 {
133 struct udevice *bus = dev->parent;
134 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
135 struct dspi *dspi = cfspi->regs;
136 struct dm_spi_slave_plat *slave_plat =
137 dev_get_parent_plat(dev);
138
139 /* Clear FIFO */
140 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
141
142 dspi_chip_unselect(slave_plat->cs[0]);
143
144 return 0;
145 }
146
coldfire_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)147 static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
148 const void *dout, void *din,
149 unsigned long flags)
150 {
151 struct udevice *bus = dev_get_parent(dev);
152 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
153 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
154 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
155 u8 *spi_rd = NULL, *spi_wr = NULL;
156 static u32 ctrl;
157 uint len = bitlen >> 3;
158
159 if (cfspi->charbit == 16) {
160 bitlen >>= 1;
161 spi_wr16 = (u16 *)dout;
162 spi_rd16 = (u16 *)din;
163 } else {
164 spi_wr = (u8 *)dout;
165 spi_rd = (u8 *)din;
166 }
167
168 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
169 ctrl |= DSPI_TFR_CONT;
170
171 ctrl = setup_ctrl(ctrl, slave_plat->cs[0]);
172
173 if (len > 1) {
174 int tmp_len = len - 1;
175
176 while (tmp_len--) {
177 if (dout) {
178 if (cfspi->charbit == 16)
179 cfspi_tx(cfspi, ctrl, *spi_wr16++);
180 else
181 cfspi_tx(cfspi, ctrl, *spi_wr++);
182 cfspi_rx(cfspi);
183 }
184
185 if (din) {
186 cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
187 if (cfspi->charbit == 16)
188 *spi_rd16++ = cfspi_rx(cfspi);
189 else
190 *spi_rd++ = cfspi_rx(cfspi);
191 }
192 }
193
194 len = 1; /* remaining byte */
195 }
196
197 if (flags & SPI_XFER_END)
198 ctrl &= ~DSPI_TFR_CONT;
199
200 if (len) {
201 if (dout) {
202 if (cfspi->charbit == 16)
203 cfspi_tx(cfspi, ctrl, *spi_wr16);
204 else
205 cfspi_tx(cfspi, ctrl, *spi_wr);
206 cfspi_rx(cfspi);
207 }
208
209 if (din) {
210 cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
211 if (cfspi->charbit == 16)
212 *spi_rd16 = cfspi_rx(cfspi);
213 else
214 *spi_rd = cfspi_rx(cfspi);
215 }
216 } else {
217 /* dummy read */
218 cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
219 cfspi_rx(cfspi);
220 }
221
222 return 0;
223 }
224
coldfire_spi_set_speed(struct udevice * bus,uint max_hz)225 static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
226 {
227 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
228 struct dspi *dspi = cfspi->regs;
229 int prescaler[] = { 2, 3, 5, 7 };
230 int scaler[] = {
231 2, 4, 6, 8,
232 16, 32, 64, 128,
233 256, 512, 1024, 2048,
234 4096, 8192, 16384, 32768
235 };
236 int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
237 int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
238 u32 bus_setup;
239
240 cfspi->baudrate = max_hz;
241
242 /* Read current setup */
243 bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
244
245 tmp = (prescaler[3] * scaler[15]);
246 /* Maximum and minimum baudrate it can handle */
247 if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
248 (cfspi->baudrate < (gd->bus_clk / tmp))) {
249 printf("Exceed baudrate limitation: Max %d - Min %d\n",
250 (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
251 return -1;
252 }
253
254 /* Activate Double Baud when it exceed 1/4 the bus clk */
255 if ((bus_setup & DSPI_CTAR_DBR) ||
256 (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
257 bus_setup |= DSPI_CTAR_DBR;
258 dbr = 1;
259 }
260
261 /* Overwrite default value set in platform configuration file */
262 if (cfspi->mode & SPI_MODE_MOD) {
263 /*
264 * Check to see if it is enabled by default in platform
265 * config, or manual setting passed by mode parameter
266 */
267 if (cfspi->mode & SPI_MODE_DBLRATE) {
268 bus_setup |= DSPI_CTAR_DBR;
269 dbr = 1;
270 }
271 }
272
273 pbrcnt = sizeof(prescaler) / sizeof(int);
274 brcnt = sizeof(scaler) / sizeof(int);
275
276 /* baudrate calculation - to closer value, may not be exact match */
277 for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
278 baud_speed = gd->bus_clk / prescaler[i];
279 for (j = 0; j < brcnt; j++) {
280 tmp = (baud_speed / scaler[j]) * (1 + dbr);
281
282 if (tmp > cfspi->baudrate)
283 diff = tmp - cfspi->baudrate;
284 else
285 diff = cfspi->baudrate - tmp;
286
287 if (diff < bestmatch) {
288 bestmatch = diff;
289 best_i = i;
290 best_j = j;
291 }
292 }
293 }
294
295 bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
296 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
297 writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
298
299 return 0;
300 }
301
coldfire_spi_set_mode(struct udevice * bus,uint mode)302 static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
303 {
304 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
305 struct dspi *dspi = cfspi->regs;
306 u32 bus_setup = 0;
307
308 cfspi->mode = mode;
309
310 if (cfspi->mode & SPI_CPOL)
311 bus_setup |= DSPI_CTAR_CPOL;
312 if (cfspi->mode & SPI_CPHA)
313 bus_setup |= DSPI_CTAR_CPHA;
314 if (cfspi->mode & SPI_LSB_FIRST)
315 bus_setup |= DSPI_CTAR_LSBFE;
316
317 /* Overwrite default value set in platform configuration file */
318 if (cfspi->mode & SPI_MODE_MOD) {
319 if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
320 bus_setup |=
321 readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
322 else
323 bus_setup |=
324 ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
325
326 /* PSCSCK, PASC, PDT */
327 bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
328 /* CSSCK, ASC, DT */
329 bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
330 } else {
331 bus_setup |=
332 (readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
333 }
334
335 cfspi->charbit =
336 ((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
337 MCF_FRM_SZ_16BIT) ? 16 : 8;
338
339 setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
340
341 return 0;
342 }
343
coldfire_spi_probe(struct udevice * bus)344 static int coldfire_spi_probe(struct udevice *bus)
345 {
346 struct coldfire_spi_plat *plat = dev_get_plat(bus);
347 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
348 struct dspi *dspi = cfspi->regs;
349 int i;
350
351 cfspi->regs = (struct dspi *)plat->regs_addr;
352
353 cfspi->baudrate = plat->speed_hz;
354 cfspi->mode = plat->mode;
355
356 for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
357 unsigned int ctar = 0;
358
359 if (plat->ctar[i][0] == 0)
360 break;
361
362 ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
363 DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
364 DSPI_CTAR_PASC(plat->ctar[i][2]) |
365 DSPI_CTAR_PDT(plat->ctar[i][3]) |
366 DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
367 DSPI_CTAR_ASC(plat->ctar[i][5]) |
368 DSPI_CTAR_DT(plat->ctar[i][6]) |
369 DSPI_CTAR_BR(plat->ctar[i][7]);
370
371 writel(ctar, &cfspi->regs->ctar[i]);
372 }
373
374 /* Default CTARs */
375 for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
376 writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
377
378 dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
379 DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
380 DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
381 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
382
383 return 0;
384 }
385
386 #if CONFIG_IS_ENABLED(OF_REAL)
coldfire_dspi_of_to_plat(struct udevice * bus)387 static int coldfire_dspi_of_to_plat(struct udevice *bus)
388 {
389 fdt_addr_t addr;
390 struct coldfire_spi_plat *plat = dev_get_plat(bus);
391 const void *blob = gd->fdt_blob;
392 int node = dev_of_offset(bus);
393 int *ctar, len;
394
395 addr = dev_read_addr(bus);
396 if (addr == FDT_ADDR_T_NONE)
397 return -ENOMEM;
398
399 plat->regs_addr = addr;
400
401 plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
402 MCF_DSPI_DEFAULT_MAX_CS);
403
404 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
405 MCF_DSPI_DEFAULT_SCK_FREQ);
406
407 plat->mode = fdtdec_get_int(blob, node, "spi-mode",
408 MCF_DSPI_DEFAULT_MODE);
409
410 memset(plat->ctar, 0, sizeof(plat->ctar));
411
412 ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
413
414 if (ctar && len) {
415 int i, q, ctar_regs;
416
417 ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
418
419 if (ctar_regs > MAX_CTAR_REGS)
420 ctar_regs = MAX_CTAR_REGS;
421
422 for (i = 0; i < ctar_regs; i++) {
423 for (q = 0; q < MAX_CTAR_FIELDS; q++)
424 plat->ctar[i][q] = *ctar++;
425 }
426 }
427
428 debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
429 (void *)plat->regs_addr,
430 plat->speed_hz, plat->num_cs, plat->mode);
431
432 return 0;
433 }
434
435 static const struct udevice_id coldfire_spi_ids[] = {
436 { .compatible = "fsl,mcf-dspi" },
437 { }
438 };
439 #endif
440
441 static const struct dm_spi_ops coldfire_spi_ops = {
442 .claim_bus = coldfire_spi_claim_bus,
443 .release_bus = coldfire_spi_release_bus,
444 .xfer = coldfire_spi_xfer,
445 .set_speed = coldfire_spi_set_speed,
446 .set_mode = coldfire_spi_set_mode,
447 };
448
449 U_BOOT_DRIVER(coldfire_spi) = {
450 .name = "spi_coldfire",
451 .id = UCLASS_SPI,
452 #if CONFIG_IS_ENABLED(OF_REAL)
453 .of_match = coldfire_spi_ids,
454 .of_to_plat = coldfire_dspi_of_to_plat,
455 .plat_auto = sizeof(struct coldfire_spi_plat),
456 #endif
457 .probe = coldfire_spi_probe,
458 .ops = &coldfire_spi_ops,
459 .priv_auto = sizeof(struct coldfire_spi_priv),
460 };
461