1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 */
5
6 #include <config.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <malloc.h>
11 #include <spi.h>
12 #include <asm/global_data.h>
13 #include <dm/device_compat.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <asm/gpio.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/mach-imx/spi.h>
22 #include <linux/printk.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 /* MX35 and older is CSPI */
27 #if defined(CONFIG_MX31)
28 #define MXC_CSPI
29 struct cspi_regs {
30 u32 rxdata;
31 u32 txdata;
32 u32 ctrl;
33 u32 intr;
34 u32 dma;
35 u32 stat;
36 u32 period;
37 u32 test;
38 };
39
40 #define MXC_CSPICTRL_EN BIT(0)
41 #define MXC_CSPICTRL_MODE BIT(1)
42 #define MXC_CSPICTRL_XCH BIT(2)
43 #define MXC_CSPICTRL_SMC BIT(3)
44 #define MXC_CSPICTRL_POL BIT(4)
45 #define MXC_CSPICTRL_PHA BIT(5)
46 #define MXC_CSPICTRL_SSCTL BIT(6)
47 #define MXC_CSPICTRL_SSPOL BIT(7)
48 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
49 #define MXC_CSPICTRL_RXOVF BIT(6)
50 #define MXC_CSPIPERIOD_32KHZ BIT(15)
51 #define MAX_SPI_BYTES 4
52 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
53 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
54 #define MXC_CSPICTRL_TC BIT(8)
55 #define MXC_CSPICTRL_MAXBITS 0x1f
56
57 #else /* MX51 and newer is ECSPI */
58 #define MXC_ECSPI
59 struct cspi_regs {
60 u32 rxdata;
61 u32 txdata;
62 u32 ctrl;
63 u32 cfg;
64 u32 intr;
65 u32 dma;
66 u32 stat;
67 u32 period;
68 };
69
70 #define MXC_CSPICTRL_EN BIT(0)
71 #define MXC_CSPICTRL_MODE BIT(1)
72 #define MXC_CSPICTRL_XCH BIT(2)
73 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
74 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
75 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
76 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
77 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
78 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
79 #define MXC_CSPICTRL_MAXBITS 0xfff
80 #define MXC_CSPICTRL_TC BIT(7)
81 #define MXC_CSPICTRL_RXOVF BIT(6)
82 #define MXC_CSPIPERIOD_32KHZ BIT(15)
83 #define MAX_SPI_BYTES 32
84
85 /* Bit position inside CTRL register to be associated with SS */
86 #define MXC_CSPICTRL_CHAN 18
87
88 /* Bit position inside CON register to be associated with SS */
89 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
90 #define MXC_CSPICON_POL 4 /* SCLK polarity */
91 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
92 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
93 #endif
94
board_spi_cs_gpio(unsigned bus,unsigned cs)95 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
96 {
97 return -1;
98 }
99
100 #define OUT MXC_GPIO_DIRECTION_OUT
101
102 #define reg_read readl
103 #define reg_write(a, v) writel(v, a)
104
105 #if !defined(CFG_SYS_SPI_MXC_WAIT)
106 #define CFG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
107 #endif
108
109 #define MAX_CS_COUNT 4
110
111 struct mxc_spi_slave {
112 struct spi_slave slave;
113 unsigned long base;
114 u32 ctrl_reg;
115 #if defined(MXC_ECSPI)
116 u32 cfg_reg;
117 #endif
118 #if CONFIG_IS_ENABLED(CLK)
119 struct clk clk;
120 #endif
121 int gpio;
122 int ss_pol;
123 unsigned int max_hz;
124 unsigned int mode;
125 struct gpio_desc ss;
126 struct gpio_desc cs_gpios[MAX_CS_COUNT];
127 struct udevice *dev;
128 };
129
to_mxc_spi_slave(struct spi_slave * slave)130 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
131 {
132 return container_of(slave, struct mxc_spi_slave, slave);
133 }
134
mxc_spi_cs_activate(struct mxc_spi_slave * mxcs)135 static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
136 {
137 #if CONFIG_IS_ENABLED(DM_SPI)
138 struct udevice *dev = mxcs->dev;
139 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
140
141 u32 cs = slave_plat->cs[0];
142
143 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
144 return;
145
146 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
147 #else
148 if (mxcs->gpio > 0)
149 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
150 #endif
151 }
152
mxc_spi_cs_deactivate(struct mxc_spi_slave * mxcs)153 static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
154 {
155 #if CONFIG_IS_ENABLED(DM_SPI)
156 struct udevice *dev = mxcs->dev;
157 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
158
159 u32 cs = slave_plat->cs[0];
160
161 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
162 return;
163
164 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
165 #else
166 if (mxcs->gpio > 0)
167 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
168 #endif
169 }
170
get_cspi_div(u32 div)171 u32 get_cspi_div(u32 div)
172 {
173 int i;
174
175 for (i = 0; i < 8; i++) {
176 if (div <= (4 << i))
177 return i;
178 }
179 return i;
180 }
181
182 #ifdef MXC_CSPI
spi_cfg_mxc(struct mxc_spi_slave * mxcs,unsigned int cs)183 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
184 {
185 unsigned int ctrl_reg;
186 u32 clk_src;
187 u32 div;
188 unsigned int max_hz = mxcs->max_hz;
189 unsigned int mode = mxcs->mode;
190
191 clk_src = mxc_get_clock(MXC_CSPI_CLK);
192
193 div = DIV_ROUND_UP(clk_src, max_hz);
194 div = get_cspi_div(div);
195
196 debug("clk %d Hz, div %d, real clk %d Hz\n",
197 max_hz, div, clk_src / (4 << div));
198
199 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
200 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
201 MXC_CSPICTRL_DATARATE(div) |
202 MXC_CSPICTRL_EN |
203 MXC_CSPICTRL_MODE;
204
205 if (mode & SPI_CPHA)
206 ctrl_reg |= MXC_CSPICTRL_PHA;
207 if (mode & SPI_CPOL)
208 ctrl_reg |= MXC_CSPICTRL_POL;
209 if (mode & SPI_CS_HIGH)
210 ctrl_reg |= MXC_CSPICTRL_SSPOL;
211 mxcs->ctrl_reg = ctrl_reg;
212
213 return 0;
214 }
215 #endif
216
217 #ifdef MXC_ECSPI
spi_cfg_mxc(struct mxc_spi_slave * mxcs,unsigned int cs)218 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
219 {
220 #if CONFIG_IS_ENABLED(CLK)
221 u32 clk_src = clk_get_rate(&mxcs->clk);
222 #else
223 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
224 #endif
225 s32 reg_ctrl, reg_config;
226 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
227 u32 pre_div = 0, post_div = 0;
228 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
229 unsigned int max_hz = mxcs->max_hz;
230 unsigned int mode = mxcs->mode;
231
232 /*
233 * Reset SPI and set all CSs to master mode, if toggling
234 * between slave and master mode we might see a glitch
235 * on the clock line
236 */
237 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
238 reg_write(®s->ctrl, reg_ctrl);
239 reg_ctrl |= MXC_CSPICTRL_EN;
240 reg_write(®s->ctrl, reg_ctrl);
241
242 if (clk_src > max_hz) {
243 pre_div = (clk_src - 1) / max_hz;
244 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
245 post_div = fls(pre_div);
246 if (post_div > 4) {
247 post_div -= 4;
248 if (post_div >= 16) {
249 printf("Error: no divider for the freq: %d\n",
250 max_hz);
251 return -1;
252 }
253 pre_div >>= post_div;
254 } else {
255 post_div = 0;
256 }
257 }
258
259 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
260 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
261 MXC_CSPICTRL_SELCHAN(cs);
262 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
263 MXC_CSPICTRL_PREDIV(pre_div);
264 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
265 MXC_CSPICTRL_POSTDIV(post_div);
266
267 if (mode & SPI_CS_HIGH)
268 ss_pol = 1;
269
270 if (mode & SPI_CPOL) {
271 sclkpol = 1;
272 sclkctl = 1;
273 }
274
275 if (mode & SPI_CPHA)
276 sclkpha = 1;
277
278 reg_config = reg_read(®s->cfg);
279
280 /*
281 * Configuration register setup
282 * The MX51 supports different setup for each SS
283 */
284 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
285 (ss_pol << (cs + MXC_CSPICON_SSPOL));
286 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
287 (sclkpol << (cs + MXC_CSPICON_POL));
288 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
289 (sclkctl << (cs + MXC_CSPICON_CTL));
290 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
291 (sclkpha << (cs + MXC_CSPICON_PHA));
292
293 debug("reg_ctrl = 0x%x\n", reg_ctrl);
294 reg_write(®s->ctrl, reg_ctrl);
295 debug("reg_config = 0x%x\n", reg_config);
296 reg_write(®s->cfg, reg_config);
297
298 /* save config register and control register */
299 mxcs->ctrl_reg = reg_ctrl;
300 mxcs->cfg_reg = reg_config;
301
302 /* clear interrupt reg */
303 reg_write(®s->intr, 0);
304 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
305
306 return 0;
307 }
308 #endif
309
spi_xchg_single(struct mxc_spi_slave * mxcs,unsigned int bitlen,const u8 * dout,u8 * din,unsigned long flags)310 int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
311 const u8 *dout, u8 *din, unsigned long flags)
312 {
313 int nbytes = DIV_ROUND_UP(bitlen, 8);
314 u32 data, cnt, i;
315 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
316 u32 ts;
317 int status;
318
319 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
320 __func__, bitlen, (ulong)dout, (ulong)din);
321
322 mxcs->ctrl_reg = (mxcs->ctrl_reg &
323 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
324 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
325
326 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
327 #ifdef MXC_ECSPI
328 reg_write(®s->cfg, mxcs->cfg_reg);
329 #endif
330
331 /* Clear interrupt register */
332 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
333
334 /*
335 * The SPI controller works only with words,
336 * check if less than a word is sent.
337 * Access to the FIFO is only 32 bit
338 */
339 if (bitlen % 32) {
340 data = 0;
341 cnt = (bitlen % 32) / 8;
342 if (dout) {
343 for (i = 0; i < cnt; i++) {
344 data = (data << 8) | (*dout++ & 0xFF);
345 }
346 }
347 debug("Sending SPI 0x%x\n", data);
348
349 reg_write(®s->txdata, data);
350 nbytes -= cnt;
351 }
352
353 data = 0;
354
355 while (nbytes > 0) {
356 data = 0;
357 if (dout) {
358 /* Buffer is not 32-bit aligned */
359 if ((unsigned long)dout & 0x03) {
360 data = 0;
361 for (i = 0; i < 4; i++)
362 data = (data << 8) | (*dout++ & 0xFF);
363 } else {
364 data = *(u32 *)dout;
365 data = cpu_to_be32(data);
366 dout += 4;
367 }
368 }
369 debug("Sending SPI 0x%x\n", data);
370 reg_write(®s->txdata, data);
371 nbytes -= 4;
372 }
373
374 /* FIFO is written, now starts the transfer setting the XCH bit */
375 reg_write(®s->ctrl, mxcs->ctrl_reg |
376 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
377
378 ts = get_timer(0);
379 status = reg_read(®s->stat);
380 /* Wait until the TC (Transfer completed) bit is set */
381 while ((status & MXC_CSPICTRL_TC) == 0) {
382 if (get_timer(ts) > CFG_SYS_SPI_MXC_WAIT) {
383 printf("spi_xchg_single: Timeout!\n");
384 return -1;
385 }
386 status = reg_read(®s->stat);
387 }
388
389 /* Transfer completed, clear any pending request */
390 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
391
392 nbytes = DIV_ROUND_UP(bitlen, 8);
393
394 if (bitlen % 32) {
395 data = reg_read(®s->rxdata);
396 cnt = (bitlen % 32) / 8;
397 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
398 debug("SPI Rx unaligned: 0x%x\n", data);
399 if (din) {
400 memcpy(din, &data, cnt);
401 din += cnt;
402 }
403 nbytes -= cnt;
404 }
405
406 while (nbytes > 0) {
407 u32 tmp;
408 tmp = reg_read(®s->rxdata);
409 data = cpu_to_be32(tmp);
410 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
411 cnt = min_t(u32, nbytes, sizeof(data));
412 if (din) {
413 memcpy(din, &data, cnt);
414 din += cnt;
415 }
416 nbytes -= cnt;
417 }
418
419 return 0;
420
421 }
422
mxc_spi_xfer_internal(struct mxc_spi_slave * mxcs,unsigned int bitlen,const void * dout,void * din,unsigned long flags)423 static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
424 unsigned int bitlen, const void *dout,
425 void *din, unsigned long flags)
426 {
427 int n_bytes = DIV_ROUND_UP(bitlen, 8);
428 int n_bits;
429 int ret;
430 u32 blk_size;
431 u8 *p_outbuf = (u8 *)dout;
432 u8 *p_inbuf = (u8 *)din;
433
434 if (!mxcs)
435 return -EINVAL;
436
437 if (flags & SPI_XFER_BEGIN)
438 mxc_spi_cs_activate(mxcs);
439
440 while (n_bytes > 0) {
441 if (n_bytes < MAX_SPI_BYTES)
442 blk_size = n_bytes;
443 else
444 blk_size = MAX_SPI_BYTES;
445
446 n_bits = blk_size * 8;
447
448 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
449
450 if (ret)
451 return ret;
452 if (dout)
453 p_outbuf += blk_size;
454 if (din)
455 p_inbuf += blk_size;
456 n_bytes -= blk_size;
457 }
458
459 if (flags & SPI_XFER_END) {
460 mxc_spi_cs_deactivate(mxcs);
461 }
462
463 return 0;
464 }
465
mxc_spi_claim_bus_internal(struct mxc_spi_slave * mxcs,int cs)466 static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
467 {
468 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
469 int ret;
470
471 reg_write(®s->rxdata, 1);
472 udelay(1);
473 ret = spi_cfg_mxc(mxcs, cs);
474 if (ret) {
475 printf("mxc_spi: cannot setup SPI controller\n");
476 return ret;
477 }
478 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
479 reg_write(®s->intr, 0);
480
481 return 0;
482 }
483
484 #if !CONFIG_IS_ENABLED(DM_SPI)
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)485 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
486 void *din, unsigned long flags)
487 {
488 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
489
490 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
491 }
492
493 /*
494 * Some SPI devices require active chip-select over multiple
495 * transactions, we achieve this using a GPIO. Still, the SPI
496 * controller has to be configured to use one of its own chipselects.
497 * To use this feature you have to implement board_spi_cs_gpio() to assign
498 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
499 * You must use some unused on this SPI controller cs between 0 and 3.
500 */
setup_cs_gpio(struct mxc_spi_slave * mxcs,unsigned int bus,unsigned int cs)501 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
502 unsigned int bus, unsigned int cs)
503 {
504 int ret;
505
506 mxcs->gpio = board_spi_cs_gpio(bus, cs);
507 if (mxcs->gpio == -1)
508 return 0;
509
510 gpio_request(mxcs->gpio, "spi-cs");
511 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
512 if (ret) {
513 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
514 return -EINVAL;
515 }
516
517 return 0;
518 }
519
520 static unsigned long spi_bases[] = {
521 MXC_SPI_BASE_ADDRESSES
522 };
523
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)524 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
525 unsigned int max_hz, unsigned int mode)
526 {
527 struct mxc_spi_slave *mxcs;
528 int ret;
529
530 if (bus >= ARRAY_SIZE(spi_bases))
531 return NULL;
532
533 if (max_hz == 0) {
534 printf("Error: desired clock is 0\n");
535 return NULL;
536 }
537
538 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
539 if (!mxcs) {
540 puts("mxc_spi: SPI Slave not allocated !\n");
541 return NULL;
542 }
543
544 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
545
546 ret = setup_cs_gpio(mxcs, bus, cs);
547 if (ret < 0) {
548 free(mxcs);
549 return NULL;
550 }
551
552 mxcs->base = spi_bases[bus];
553 mxcs->max_hz = max_hz;
554 mxcs->mode = mode;
555
556 return &mxcs->slave;
557 }
558
spi_free_slave(struct spi_slave * slave)559 void spi_free_slave(struct spi_slave *slave)
560 {
561 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
562
563 free(mxcs);
564 }
565
spi_claim_bus(struct spi_slave * slave)566 int spi_claim_bus(struct spi_slave *slave)
567 {
568 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
569
570 return mxc_spi_claim_bus_internal(mxcs, slave->cs);
571 }
572
spi_release_bus(struct spi_slave * slave)573 void spi_release_bus(struct spi_slave *slave)
574 {
575 /* TODO: Shut the controller down */
576 }
577 #else
578
mxc_spi_probe(struct udevice * bus)579 static int mxc_spi_probe(struct udevice *bus)
580 {
581 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
582 int ret;
583 int i;
584
585 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
586 ARRAY_SIZE(mxcs->cs_gpios), 0);
587 if (ret < 0) {
588 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
589 return ret;
590 }
591
592 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
593 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
594 continue;
595
596 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
597 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
598 if (ret) {
599 dev_err(bus, "Setting cs %d error\n", i);
600 return ret;
601 }
602 }
603
604 mxcs->base = dev_read_addr(bus);
605 if (mxcs->base == FDT_ADDR_T_NONE)
606 return -ENODEV;
607
608 #if CONFIG_IS_ENABLED(CLK)
609 ret = clk_get_by_index(bus, 0, &mxcs->clk);
610 if (ret)
611 return ret;
612
613 clk_enable(&mxcs->clk);
614
615 mxcs->max_hz = clk_get_rate(&mxcs->clk);
616 #else
617 int node = dev_of_offset(bus);
618 const void *blob = gd->fdt_blob;
619 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
620 20000000);
621 #endif
622
623 return 0;
624 }
625
mxc_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)626 static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
627 const void *dout, void *din, unsigned long flags)
628 {
629 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
630
631 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
632 }
633
mxc_spi_claim_bus(struct udevice * dev)634 static int mxc_spi_claim_bus(struct udevice *dev)
635 {
636 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
637 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
638
639 mxcs->dev = dev;
640
641 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs[0]);
642 }
643
mxc_spi_release_bus(struct udevice * dev)644 static int mxc_spi_release_bus(struct udevice *dev)
645 {
646 return 0;
647 }
648
mxc_spi_set_speed(struct udevice * bus,uint speed)649 static int mxc_spi_set_speed(struct udevice *bus, uint speed)
650 {
651 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
652
653 mxcs->max_hz = speed;
654
655 return 0;
656 }
657
mxc_spi_set_mode(struct udevice * bus,uint mode)658 static int mxc_spi_set_mode(struct udevice *bus, uint mode)
659 {
660 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
661
662 mxcs->mode = mode;
663 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
664
665 return 0;
666 }
667
668 static const struct dm_spi_ops mxc_spi_ops = {
669 .claim_bus = mxc_spi_claim_bus,
670 .release_bus = mxc_spi_release_bus,
671 .xfer = mxc_spi_xfer,
672 .set_speed = mxc_spi_set_speed,
673 .set_mode = mxc_spi_set_mode,
674 };
675
676 static const struct udevice_id mxc_spi_ids[] = {
677 { .compatible = "fsl,imx51-ecspi" },
678 { .compatible = "fsl,imx6ul-ecspi" },
679 { }
680 };
681
682 U_BOOT_DRIVER(mxc_spi) = {
683 .name = "mxc_spi",
684 .id = UCLASS_SPI,
685 .of_match = mxc_spi_ids,
686 .ops = &mxc_spi_ops,
687 .plat_auto = sizeof(struct mxc_spi_slave),
688 .probe = mxc_spi_probe,
689 };
690 #endif
691