1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4  */
5 
6 #include <dm.h>
7 #include <errno.h>
8 #include <sysreset.h>
9 #include <asm/arch-rockchip/clock.h>
10 #include <asm/arch-rockchip/cru_rk3328.h>
11 #include <asm/arch-rockchip/hardware.h>
12 #include <linux/err.h>
13 
rockchip_sysreset_request(struct udevice * dev,enum sysreset_t type)14 int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
15 {
16 	struct sysreset_reg *offset = dev_get_priv(dev);
17 	unsigned long cru_base = (unsigned long)rockchip_get_cru();
18 
19 	if (IS_ERR_VALUE(cru_base))
20 		return (int)cru_base;
21 
22 	switch (type) {
23 	case SYSRESET_WARM:
24 		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
25 		break;
26 	case SYSRESET_COLD:
27 		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
28 		break;
29 	default:
30 		return -EPROTONOSUPPORT;
31 	}
32 
33 	return -EINPROGRESS;
34 }
35 
36 static struct sysreset_ops rockchip_sysreset = {
37 	.request	= rockchip_sysreset_request,
38 };
39 
40 U_BOOT_DRIVER(sysreset_rockchip) = {
41 	.name	= "rockchip_sysreset",
42 	.id	= UCLASS_SYSRESET,
43 	.ops	= &rockchip_sysreset,
44 };
45