1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Microchip Corporation
4 *
5 * Author: Clément Léger <clement.leger@bootlin.com>
6 */
7
8 #include <clk.h>
9 #include <dm.h>
10 #include <timer.h>
11 #include <asm/io.h>
12 #include <linux/bitops.h>
13
14 #define TCB_CHAN(chan) ((chan) * 0x40)
15
16 #define TCB_CCR(chan) (0x0 + TCB_CHAN(chan))
17 #define TCB_CCR_CLKEN (1 << 0)
18
19 #define TCB_CMR(chan) (0x4 + TCB_CHAN(chan))
20 #define TCB_CMR_WAVE (1 << 15)
21 #define TCB_CMR_TIMER_CLOCK2 1
22 #define TCB_CMR_XC1 6
23 #define TCB_CMR_ACPA_SET (1 << 16)
24 #define TCB_CMR_ACPC_CLEAR (2 << 18)
25
26 #define TCB_CV(chan) (0x10 + TCB_CHAN(chan))
27
28 #define TCB_RA(chan) (0x14 + TCB_CHAN(chan))
29 #define TCB_RC(chan) (0x1c + TCB_CHAN(chan))
30
31 #define TCB_IDR(chan) (0x28 + TCB_CHAN(chan))
32
33 #define TCB_BCR 0xc0
34 #define TCB_BCR_SYNC (1 << 0)
35
36 #define TCB_BMR 0xc4
37 #define TCB_BMR_TC1XC1S_TIOA0 (2 << 2)
38
39 #define TCB_WPMR 0xe4
40 #define TCB_WPMR_WAKEY 0x54494d
41
42 #define TCB_CLK_DIVISOR 8
43 struct atmel_tcb_plat {
44 void __iomem *base;
45 };
46
atmel_tcb_get_count(struct udevice * dev)47 static u64 atmel_tcb_get_count(struct udevice *dev)
48 {
49 struct atmel_tcb_plat *plat = dev_get_plat(dev);
50 u64 cv0 = 0;
51 u64 cv1 = 0;
52
53 do {
54 cv1 = readl(plat->base + TCB_CV(1));
55 cv0 = readl(plat->base + TCB_CV(0));
56 } while (readl(plat->base + TCB_CV(1)) != cv1);
57
58 cv0 |= cv1 << 32;
59
60 return cv0;
61 }
62
atmel_tcb_configure(void __iomem * base)63 static void atmel_tcb_configure(void __iomem *base)
64 {
65 /* Disable write protection */
66 writel(TCB_WPMR_WAKEY, base + TCB_WPMR);
67
68 /* Disable all irqs for both channel 0 & 1 */
69 writel(0xff, base + TCB_IDR(0));
70 writel(0xff, base + TCB_IDR(1));
71
72 /*
73 * In order to avoid wrapping, use a 64 bit counter by chaining
74 * two channels.
75 * Channel 0 is configured to generate a clock on TIOA0 which is cleared
76 * when reaching 0x80000000 and set when reaching 0.
77 */
78 writel(TCB_CMR_TIMER_CLOCK2 | TCB_CMR_WAVE | TCB_CMR_ACPA_SET
79 | TCB_CMR_ACPC_CLEAR, base + TCB_CMR(0));
80 writel(0x80000000, base + TCB_RC(0));
81 writel(0x1, base + TCB_RA(0));
82 writel(TCB_CCR_CLKEN, base + TCB_CCR(0));
83
84 /* Channel 1 is configured to use TIOA0 as input */
85 writel(TCB_CMR_XC1 | TCB_CMR_WAVE, base + TCB_CMR(1));
86 writel(TCB_CCR_CLKEN, base + TCB_CCR(1));
87
88 /* Set XC1 input to be TIOA0 (ie output of Channel 0) */
89 writel(TCB_BMR_TC1XC1S_TIOA0, base + TCB_BMR);
90
91 /* Sync & start all timers */
92 writel(TCB_BCR_SYNC, base + TCB_BCR);
93 }
94
atmel_tcb_probe(struct udevice * dev)95 static int atmel_tcb_probe(struct udevice *dev)
96 {
97 struct atmel_tcb_plat *plat = dev_get_plat(dev);
98 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
99 struct clk clk;
100 ulong clk_rate;
101 int ret;
102
103 if (!device_is_compatible(dev->parent, "atmel,sama5d2-tcb"))
104 return -EINVAL;
105
106 /* Currently, we only support channel 0 and 1 to be chained */
107 if (dev_read_addr_index(dev, 0) != 0 &&
108 dev_read_addr_index(dev, 1) != 1) {
109 printf("Error: only chained timers 0 and 1 are supported\n");
110 return -EINVAL;
111 }
112
113 ret = clk_get_by_name(dev->parent, "t0_clk", &clk);
114 if (ret)
115 return -EINVAL;
116
117 ret = clk_enable(&clk);
118 if (ret)
119 return ret;
120
121 clk_rate = clk_get_rate(&clk);
122 if (!clk_rate) {
123 clk_disable(&clk);
124 return -EINVAL;
125 }
126
127 uc_priv->clock_rate = clk_rate / TCB_CLK_DIVISOR;
128
129 atmel_tcb_configure(plat->base);
130
131 return 0;
132 }
133
atmel_tcb_of_to_plat(struct udevice * dev)134 static int atmel_tcb_of_to_plat(struct udevice *dev)
135 {
136 struct atmel_tcb_plat *plat = dev_get_plat(dev);
137
138 plat->base = dev_read_addr_ptr(dev->parent);
139
140 return 0;
141 }
142
143 static const struct timer_ops atmel_tcb_ops = {
144 .get_count = atmel_tcb_get_count,
145 };
146
147 static const struct udevice_id atmel_tcb_ids[] = {
148 { .compatible = "atmel,tcb-timer" },
149 { }
150 };
151
152 U_BOOT_DRIVER(atmel_tcb) = {
153 .name = "atmel_tcb",
154 .id = UCLASS_TIMER,
155 .of_match = atmel_tcb_ids,
156 .of_to_plat = atmel_tcb_of_to_plat,
157 .plat_auto = sizeof(struct atmel_tcb_plat),
158 .probe = atmel_tcb_probe,
159 .ops = &atmel_tcb_ops,
160 };
161