1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
4 */
5
6 #include <bootstage.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <init.h>
10 #include <timer.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15
16 #define CNT_CNTRL_RESET BIT(4)
17
18 struct cadence_ttc_regs {
19 u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
20 u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
21 u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
22 u32 counter_cntrl1; /* 0xC - Counter Control 1 */
23 u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
24 u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
25 u32 counter_val1; /* 0x18 - Counter Control 1 */
26 u32 counter_val2; /* 0x1C - Counter Control 2 */
27 u32 counter_val3; /* 0x20 - Counter Control 3 */
28 u32 reserved[15];
29 u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
30 u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
31 u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
32 };
33
34 struct cadence_ttc_priv {
35 struct cadence_ttc_regs *regs;
36 };
37
38 #if CONFIG_IS_ENABLED(BOOTSTAGE)
timer_get_boot_us(void)39 ulong timer_get_boot_us(void)
40 {
41 u64 ticks = 0;
42 u32 rate = 1;
43 u64 us;
44 int ret;
45
46 ret = dm_timer_init();
47 if (!ret) {
48 /* The timer is available */
49 rate = timer_get_rate(gd->timer);
50 timer_get_count(gd->timer, &ticks);
51 } else {
52 return 0;
53 }
54
55 us = (ticks * 1000) / rate;
56 return us;
57 }
58 #endif
59
cadence_ttc_get_count(struct udevice * dev)60 static u64 cadence_ttc_get_count(struct udevice *dev)
61 {
62 struct cadence_ttc_priv *priv = dev_get_priv(dev);
63
64 return readl(&priv->regs->counter_val1);
65 }
66
cadence_ttc_probe(struct udevice * dev)67 static int cadence_ttc_probe(struct udevice *dev)
68 {
69 struct cadence_ttc_priv *priv = dev_get_priv(dev);
70
71 /* Disable interrupts for sure */
72 writel(0, &priv->regs->interrupt_enable1);
73 writel(0, &priv->regs->interrupt_enable2);
74 writel(0, &priv->regs->interrupt_enable3);
75
76 /* Make sure that clocks are configured properly without prescaller */
77 writel(0, &priv->regs->clk_cntrl1);
78 writel(0, &priv->regs->clk_cntrl2);
79 writel(0, &priv->regs->clk_cntrl3);
80
81 /* Reset and enable this counter */
82 writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
83
84 return 0;
85 }
86
cadence_ttc_of_to_plat(struct udevice * dev)87 static int cadence_ttc_of_to_plat(struct udevice *dev)
88 {
89 struct cadence_ttc_priv *priv = dev_get_priv(dev);
90
91 priv->regs = map_physmem(dev_read_addr(dev),
92 sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
93 if (IS_ERR(priv->regs))
94 return PTR_ERR(priv->regs);
95
96 return 0;
97 }
98
cadence_ttc_bind(struct udevice * dev)99 static int cadence_ttc_bind(struct udevice *dev)
100 {
101 const char *cells;
102
103 cells = dev_read_prop(dev, "#pwm-cells", NULL);
104 if (cells)
105 return -ENODEV;
106
107 return 0;
108 }
109
110 static const struct timer_ops cadence_ttc_ops = {
111 .get_count = cadence_ttc_get_count,
112 };
113
114 static const struct udevice_id cadence_ttc_ids[] = {
115 { .compatible = "cdns,ttc" },
116 {}
117 };
118
119 U_BOOT_DRIVER(cadence_ttc) = {
120 .name = "cadence_ttc",
121 .id = UCLASS_TIMER,
122 .of_match = cadence_ttc_ids,
123 .of_to_plat = cadence_ttc_of_to_plat,
124 .priv_auto = sizeof(struct cadence_ttc_priv),
125 .probe = cadence_ttc_probe,
126 .ops = &cadence_ttc_ops,
127 .bind = cadence_ttc_bind,
128 };
129