1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Designware APB Timer driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
6 */
7
8 #include <dm.h>
9 #include <clk.h>
10 #include <dt-structs.h>
11 #include <malloc.h>
12 #include <reset.h>
13 #include <timer.h>
14 #include <dm/device_compat.h>
15
16 #include <asm/io.h>
17 #include <asm/arch/timer.h>
18
19 #define DW_APB_LOAD_VAL 0x0
20 #define DW_APB_CURR_VAL 0x4
21 #define DW_APB_CTRL 0x8
22
23 struct dw_apb_timer_priv {
24 uintptr_t regs;
25 struct reset_ctl_bulk resets;
26 };
27
28 struct dw_apb_timer_plat {
29 #if CONFIG_IS_ENABLED(OF_PLATDATA)
30 struct dtd_snps_dw_apb_timer dtplat;
31 #endif
32 };
33
dw_apb_timer_get_count(struct udevice * dev)34 static u64 dw_apb_timer_get_count(struct udevice *dev)
35 {
36 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
37
38 /*
39 * The DW APB counter counts down, but this function
40 * requires the count to be incrementing. Invert the
41 * result.
42 */
43 return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
44 }
45
dw_apb_timer_probe(struct udevice * dev)46 static int dw_apb_timer_probe(struct udevice *dev)
47 {
48 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
49 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
50 struct clk clk;
51 int ret;
52 #if CONFIG_IS_ENABLED(OF_PLATDATA)
53 struct dw_apb_timer_plat *plat = dev_get_plat(dev);
54 struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat;
55
56 priv->regs = dtplat->reg[0];
57
58 ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk);
59 if (ret < 0)
60 return ret;
61
62 uc_priv->clock_rate = dtplat->clock_frequency;
63 #endif
64 if (CONFIG_IS_ENABLED(OF_REAL)) {
65 ret = reset_get_bulk(dev, &priv->resets);
66 if (ret)
67 dev_warn(dev, "Can't get reset: %d\n", ret);
68 else
69 reset_deassert_bulk(&priv->resets);
70
71 ret = clk_get_by_index(dev, 0, &clk);
72 if (ret)
73 return ret;
74
75 uc_priv->clock_rate = clk_get_rate(&clk);
76 }
77
78 /* init timer */
79 writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
80 writel(0xffffffff, priv->regs + DW_APB_CURR_VAL);
81 setbits_le32(priv->regs + DW_APB_CTRL, 0x3);
82
83 return 0;
84 }
85
dw_apb_timer_of_to_plat(struct udevice * dev)86 static int dw_apb_timer_of_to_plat(struct udevice *dev)
87 {
88 if (CONFIG_IS_ENABLED(OF_REAL)) {
89 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
90
91 priv->regs = dev_read_addr(dev);
92 }
93
94 return 0;
95 }
96
dw_apb_timer_remove(struct udevice * dev)97 static int dw_apb_timer_remove(struct udevice *dev)
98 {
99 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
100
101 return reset_release_bulk(&priv->resets);
102 }
103
104 static const struct timer_ops dw_apb_timer_ops = {
105 .get_count = dw_apb_timer_get_count,
106 };
107
108 static const struct udevice_id dw_apb_timer_ids[] = {
109 { .compatible = "snps,dw-apb-timer" },
110 {}
111 };
112
113 U_BOOT_DRIVER(snps_dw_apb_timer) = {
114 .name = "snps_dw_apb_timer",
115 .id = UCLASS_TIMER,
116 .ops = &dw_apb_timer_ops,
117 .probe = dw_apb_timer_probe,
118 .of_match = dw_apb_timer_ids,
119 .of_to_plat = dw_apb_timer_of_to_plat,
120 .remove = dw_apb_timer_remove,
121 .priv_auto = sizeof(struct dw_apb_timer_priv),
122 .plat_auto = sizeof(struct dw_apb_timer_plat),
123 };
124