1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * TI OMAP timer driver
4 *
5 * Copyright (C) 2015, Texas Instruments, Incorporated
6 */
7
8 #include <dm.h>
9 #include <errno.h>
10 #include <timer.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/omap_common.h>
14 #include <linux/bitops.h>
15
16 /* Timer register bits */
17 #define TCLR_START BIT(0) /* Start=1 */
18 #define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */
19 #define TCLR_PRE_EN BIT(5) /* Pre-scaler enable */
20 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
21
22 struct omap_gptimer_regs {
23 unsigned int tidr; /* offset 0x00 */
24 unsigned char res1[12];
25 unsigned int tiocp_cfg; /* offset 0x10 */
26 unsigned char res2[12];
27 unsigned int tier; /* offset 0x20 */
28 unsigned int tistatr; /* offset 0x24 */
29 unsigned int tistat; /* offset 0x28 */
30 unsigned int tisr; /* offset 0x2c */
31 unsigned int tcicr; /* offset 0x30 */
32 unsigned int twer; /* offset 0x34 */
33 unsigned int tclr; /* offset 0x38 */
34 unsigned int tcrr; /* offset 0x3c */
35 unsigned int tldr; /* offset 0x40 */
36 unsigned int ttgr; /* offset 0x44 */
37 unsigned int twpc; /* offset 0x48 */
38 unsigned int tmar; /* offset 0x4c */
39 unsigned int tcar1; /* offset 0x50 */
40 unsigned int tscir; /* offset 0x54 */
41 unsigned int tcar2; /* offset 0x58 */
42 };
43
44 /* Omap Timer Priv */
45 struct omap_timer_priv {
46 struct omap_gptimer_regs *regs;
47 };
48
omap_timer_get_count(struct udevice * dev)49 static u64 omap_timer_get_count(struct udevice *dev)
50 {
51 struct omap_timer_priv *priv = dev_get_priv(dev);
52
53 return timer_conv_64(readl(&priv->regs->tcrr));
54 }
55
omap_timer_probe(struct udevice * dev)56 static int omap_timer_probe(struct udevice *dev)
57 {
58 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
59 struct omap_timer_priv *priv = dev_get_priv(dev);
60
61 if (!uc_priv->clock_rate)
62 uc_priv->clock_rate = V_SCLK;
63
64 uc_priv->clock_rate /= (2 << SYS_PTV);
65
66 /* start the counter ticking up, reload value on overflow */
67 writel(0, &priv->regs->tldr);
68 writel(0, &priv->regs->tcrr);
69 /* enable timer */
70 writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
71 TCLR_START, &priv->regs->tclr);
72
73 return 0;
74 }
75
omap_timer_of_to_plat(struct udevice * dev)76 static int omap_timer_of_to_plat(struct udevice *dev)
77 {
78 struct omap_timer_priv *priv = dev_get_priv(dev);
79
80 priv->regs = map_physmem(dev_read_addr(dev),
81 sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
82
83 return 0;
84 }
85
86 #if CONFIG_IS_ENABLED(BOOTSTAGE)
timer_get_boot_us(void)87 ulong timer_get_boot_us(void)
88 {
89 u64 ticks = 0;
90 u32 rate = 1;
91 u64 us;
92 int ret;
93
94 ret = dm_timer_init();
95 if (!ret) {
96 /* The timer is available */
97 rate = timer_get_rate(gd->timer);
98 timer_get_count(gd->timer, &ticks);
99 } else {
100 return 0;
101 }
102
103 us = (ticks * 1000) / rate;
104 return us;
105 }
106 #endif
107
108 static const struct timer_ops omap_timer_ops = {
109 .get_count = omap_timer_get_count,
110 };
111
112 static const struct udevice_id omap_timer_ids[] = {
113 { .compatible = "ti,am335x-timer" },
114 { .compatible = "ti,am4372-timer" },
115 { .compatible = "ti,omap5430-timer" },
116 { .compatible = "ti,am654-timer" },
117 {}
118 };
119
120 U_BOOT_DRIVER(omap_timer) = {
121 .name = "omap_timer",
122 .id = UCLASS_TIMER,
123 .of_match = omap_timer_ids,
124 .of_to_plat = omap_timer_of_to_plat,
125 .priv_auto = sizeof(struct omap_timer_priv),
126 .probe = omap_timer_probe,
127 .ops = &omap_timer_ops,
128 };
129