1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6 #include <bootstage.h>
7 #include <dm.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <dm/ofnode.h>
12 #include <mapmem.h>
13 #include <asm/arch-rockchip/timer.h>
14 #include <dt-structs.h>
15 #include <timer.h>
16 #include <asm/io.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #if CONFIG_IS_ENABLED(OF_PLATDATA)
21 struct rockchip_timer_plat {
22 struct dtd_rockchip_rk3288_timer dtd;
23 };
24 #endif
25
26 /* Driver private data. Contains timer id. Could be either 0 or 1. */
27 struct rockchip_timer_priv {
28 struct rk_timer *timer;
29 };
30
rockchip_timer_get_curr_value(struct rk_timer * timer)31 static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
32 {
33 uint64_t timebase_h, timebase_l;
34 uint64_t cntr;
35
36 timebase_l = readl(&timer->timer_curr_value0);
37 timebase_h = readl(&timer->timer_curr_value1);
38
39 cntr = timebase_h << 32 | timebase_l;
40 return cntr;
41 }
42
43 #if CONFIG_IS_ENABLED(BOOTSTAGE)
timer_get_boot_us(void)44 ulong timer_get_boot_us(void)
45 {
46 uint64_t ticks = 0;
47 uint32_t rate;
48 uint64_t us;
49 int ret;
50
51 ret = dm_timer_init();
52
53 if (!ret) {
54 /* The timer is available */
55 rate = timer_get_rate(gd->timer);
56 timer_get_count(gd->timer, &ticks);
57 } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
58 /* We have been called so early that the DM is not ready,... */
59 ofnode node = offset_to_ofnode(-1);
60 struct rk_timer *timer = NULL;
61
62 /*
63 * ... so we try to access the raw timer, if it is specified
64 * via the tick-timer property in /chosen.
65 */
66 node = ofnode_get_chosen_node("tick-timer");
67 if (!ofnode_valid(node)) {
68 debug("%s: no /chosen/tick-timer\n", __func__);
69 return 0;
70 }
71
72 timer = (struct rk_timer *)ofnode_get_addr(node);
73
74 /* This timer is down-counting */
75 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
76 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
77 debug("%s: could not read clock-frequency\n", __func__);
78 return 0;
79 }
80 } else {
81 return 0;
82 }
83
84 us = (ticks * 1000) / rate;
85 return us;
86 }
87 #endif
88
rockchip_timer_get_count(struct udevice * dev)89 static u64 rockchip_timer_get_count(struct udevice *dev)
90 {
91 struct rockchip_timer_priv *priv = dev_get_priv(dev);
92 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
93
94 /* timers are down-counting */
95 return ~0ull - cntr;
96 }
97
rockchip_clk_of_to_plat(struct udevice * dev)98 static int rockchip_clk_of_to_plat(struct udevice *dev)
99 {
100 if (CONFIG_IS_ENABLED(OF_REAL)) {
101 struct rockchip_timer_priv *priv = dev_get_priv(dev);
102
103 priv->timer = dev_read_addr_ptr(dev);
104 if (!priv->timer)
105 return -ENOENT;
106 }
107
108 return 0;
109 }
110
rockchip_timer_start(struct udevice * dev)111 static int rockchip_timer_start(struct udevice *dev)
112 {
113 struct rockchip_timer_priv *priv = dev_get_priv(dev);
114 const uint64_t reload_val = ~0uLL;
115 const uint32_t reload_val_l = reload_val & 0xffffffff;
116 const uint32_t reload_val_h = reload_val >> 32;
117
118 /* don't reinit, if the timer is already running and set up */
119 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
120 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
121 (readl(&priv->timer->timer_load_count1) == reload_val_h))
122 return 0;
123
124 /* disable timer and reset all control */
125 writel(0, &priv->timer->timer_ctrl_reg);
126 /* write reload value */
127 writel(reload_val_l, &priv->timer->timer_load_count0);
128 writel(reload_val_h, &priv->timer->timer_load_count1);
129 /* enable timer */
130 writel(1, &priv->timer->timer_ctrl_reg);
131
132 return 0;
133 }
134
rockchip_timer_probe(struct udevice * dev)135 static int rockchip_timer_probe(struct udevice *dev)
136 {
137 #if CONFIG_IS_ENABLED(OF_PLATDATA)
138 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
139 struct rockchip_timer_priv *priv = dev_get_priv(dev);
140 struct rockchip_timer_plat *plat = dev_get_plat(dev);
141
142 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
143 uc_priv->clock_rate = plat->dtd.clock_frequency;
144 #endif
145
146 return rockchip_timer_start(dev);
147 }
148
149 static const struct timer_ops rockchip_timer_ops = {
150 .get_count = rockchip_timer_get_count,
151 };
152
153 static const struct udevice_id rockchip_timer_ids[] = {
154 { .compatible = "rockchip,rk3288-timer" },
155 {}
156 };
157
158 U_BOOT_DRIVER(rockchip_rk3288_timer) = {
159 .name = "rockchip_rk3288_timer",
160 .id = UCLASS_TIMER,
161 .of_match = rockchip_timer_ids,
162 .probe = rockchip_timer_probe,
163 .ops = &rockchip_timer_ops,
164 .priv_auto = sizeof(struct rockchip_timer_priv),
165 #if CONFIG_IS_ENABLED(OF_PLATDATA)
166 .plat_auto = sizeof(struct rockchip_timer_plat),
167 #endif
168 .of_to_plat = rockchip_clk_of_to_plat,
169 };
170