1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2012 The Chromium OS Authors.
4 *
5 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 */
8
9 #include <bootstage.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <time.h>
14 #include <timer.h>
15 #include <asm/cpu.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/i8254.h>
19 #include <asm/ibmpc.h>
20 #include <asm/msr.h>
21 #include <asm/u-boot-x86.h>
22 #include <linux/delay.h>
23
24 #define MAX_NUM_FREQS 9
25
26 #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
27 #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
28 #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
29 #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
30 #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
31 #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 /*
36 * native_calibrate_tsc
37 * Determine TSC frequency via CPUID, else return 0.
38 */
native_calibrate_tsc(void)39 static unsigned long native_calibrate_tsc(void)
40 {
41 struct cpuid_result tsc_info;
42 unsigned int crystal_freq;
43
44 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
45 return 0;
46
47 if (cpuid_eax(0) < 0x15)
48 return 0;
49
50 tsc_info = cpuid(0x15);
51
52 if (tsc_info.ebx == 0 || tsc_info.eax == 0)
53 return 0;
54
55 crystal_freq = tsc_info.ecx / 1000;
56 if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
57 switch (gd->arch.x86_model) {
58 case INTEL_FAM6_SKYLAKE_MOBILE:
59 case INTEL_FAM6_SKYLAKE_DESKTOP:
60 case INTEL_FAM6_KABYLAKE_MOBILE:
61 case INTEL_FAM6_KABYLAKE_DESKTOP:
62 crystal_freq = 24000; /* 24.0 MHz */
63 break;
64 case INTEL_FAM6_ATOM_GOLDMONT_X:
65 crystal_freq = 25000; /* 25.0 MHz */
66 break;
67 case INTEL_FAM6_ATOM_GOLDMONT:
68 crystal_freq = 19200; /* 19.2 MHz */
69 break;
70 default:
71 return 0;
72 }
73 }
74
75 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
76 }
77
cpu_mhz_from_cpuid(void)78 static unsigned long cpu_mhz_from_cpuid(void)
79 {
80 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
81 return 0;
82
83 if (cpuid_eax(0) < 0x16)
84 return 0;
85
86 return cpuid_eax(0x15);
87 }
88
89 /*
90 * According to Intel 64 and IA-32 System Programming Guide,
91 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
92 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
93 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
94 * so we need manually differentiate SoC families. This is what the
95 * field msr_plat does.
96 */
97 struct freq_desc {
98 u8 x86_family; /* CPU family */
99 u8 x86_model; /* model */
100 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
101 u8 msr_plat;
102 u32 freqs[MAX_NUM_FREQS];
103 };
104
105 static struct freq_desc freq_desc_tables[] = {
106 /* PNW */
107 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
108 /* CLV+ */
109 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
110 /* TNG - Intel Atom processor Z3400 series */
111 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
112 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
113 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
114 /* ANN - Intel Atom processor Z3500 series */
115 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
116 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
117 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
118 80000, 93300, 90000, 88900, 87500 } },
119 /* Ivybridge */
120 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
121 };
122
match_cpu(u8 family,u8 model)123 static int match_cpu(u8 family, u8 model)
124 {
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
128 if ((family == freq_desc_tables[i].x86_family) &&
129 (model == freq_desc_tables[i].x86_model))
130 return i;
131 }
132
133 return -1;
134 }
135
136 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
137 #define id_to_freq(cpu_index, freq_id) \
138 (freq_desc_tables[cpu_index].freqs[freq_id])
139
140 /*
141 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
142 * reliable and the frequency is known (provided by HW).
143 *
144 * On these platforms PIT/HPET is generally not available so calibration won't
145 * work at all and there is no other clocksource to act as a watchdog for the
146 * TSC, so we have no other choice than to trust it.
147 *
148 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
149 */
cpu_mhz_from_msr(void)150 static unsigned long __maybe_unused cpu_mhz_from_msr(void)
151 {
152 u32 lo, hi, ratio, freq_id, freq;
153 unsigned long res;
154 int cpu_index;
155
156 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
157 return 0;
158
159 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
160 if (cpu_index < 0)
161 return 0;
162
163 if (freq_desc_tables[cpu_index].msr_plat) {
164 rdmsr(MSR_PLATFORM_INFO, lo, hi);
165 ratio = (lo >> 8) & 0xff;
166 } else {
167 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
168 ratio = (hi >> 8) & 0x1f;
169 }
170 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
171
172 if (freq_desc_tables[cpu_index].msr_plat == 2) {
173 /* TODO: Figure out how best to deal with this */
174 freq = 100000;
175 debug("Using frequency: %u KHz\n", freq);
176 } else {
177 /* Get FSB FREQ ID */
178 rdmsr(MSR_FSB_FREQ, lo, hi);
179 freq_id = lo & 0x7;
180 freq = id_to_freq(cpu_index, freq_id);
181 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
182 freq_id, freq);
183 }
184
185 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
186 res = freq * ratio / 1000;
187 debug("TSC runs at %lu MHz\n", res);
188
189 return res;
190 }
191
192 /*
193 * This reads the current MSB of the PIT counter, and
194 * checks if we are running on sufficiently fast and
195 * non-virtualized hardware.
196 *
197 * Our expectations are:
198 *
199 * - the PIT is running at roughly 1.19MHz
200 *
201 * - each IO is going to take about 1us on real hardware,
202 * but we allow it to be much faster (by a factor of 10) or
203 * _slightly_ slower (ie we allow up to a 2us read+counter
204 * update - anything else implies a unacceptably slow CPU
205 * or PIT for the fast calibration to work.
206 *
207 * - with 256 PIT ticks to read the value, we have 214us to
208 * see the same MSB (and overhead like doing a single TSC
209 * read per MSB value etc).
210 *
211 * - We're doing 2 reads per loop (LSB, MSB), and we expect
212 * them each to take about a microsecond on real hardware.
213 * So we expect a count value of around 100. But we'll be
214 * generous, and accept anything over 50.
215 *
216 * - if the PIT is stuck, and we see *many* more reads, we
217 * return early (and the next caller of pit_expect_msb()
218 * then consider it a failure when they don't see the
219 * next expected value).
220 *
221 * These expectations mean that we know that we have seen the
222 * transition from one expected value to another with a fairly
223 * high accuracy, and we didn't miss any events. We can thus
224 * use the TSC value at the transitions to calculate a pretty
225 * good value for the TSC frequencty.
226 */
pit_verify_msb(unsigned char val)227 static inline int pit_verify_msb(unsigned char val)
228 {
229 /* Ignore LSB */
230 inb(0x42);
231 return inb(0x42) == val;
232 }
233
pit_expect_msb(unsigned char val,u64 * tscp,unsigned long * deltap)234 static inline int pit_expect_msb(unsigned char val, u64 *tscp,
235 unsigned long *deltap)
236 {
237 int count;
238 u64 tsc = 0, prev_tsc = 0;
239
240 for (count = 0; count < 50000; count++) {
241 if (!pit_verify_msb(val))
242 break;
243 prev_tsc = tsc;
244 tsc = rdtsc();
245 }
246 *deltap = rdtsc() - prev_tsc;
247 *tscp = tsc;
248
249 /*
250 * We require _some_ success, but the quality control
251 * will be based on the error terms on the TSC values.
252 */
253 return count > 5;
254 }
255
256 /*
257 * How many MSB values do we want to see? We aim for
258 * a maximum error rate of 500ppm (in practice the
259 * real error is much smaller), but refuse to spend
260 * more than 50ms on it.
261 */
262 #define MAX_QUICK_PIT_MS 50
263 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
264
quick_pit_calibrate(void)265 static unsigned long __maybe_unused quick_pit_calibrate(void)
266 {
267 int i;
268 u64 tsc, delta;
269 unsigned long d1, d2;
270
271 /* Set the Gate high, disable speaker */
272 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
273
274 /*
275 * Counter 2, mode 0 (one-shot), binary count
276 *
277 * NOTE! Mode 2 decrements by two (and then the
278 * output is flipped each time, giving the same
279 * final output frequency as a decrement-by-one),
280 * so mode 0 is much better when looking at the
281 * individual counts.
282 */
283 outb(0xb0, 0x43);
284
285 /* Start at 0xffff */
286 outb(0xff, 0x42);
287 outb(0xff, 0x42);
288
289 /*
290 * The PIT starts counting at the next edge, so we
291 * need to delay for a microsecond. The easiest way
292 * to do that is to just read back the 16-bit counter
293 * once from the PIT.
294 */
295 pit_verify_msb(0);
296
297 if (pit_expect_msb(0xff, &tsc, &d1)) {
298 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
299 if (!pit_expect_msb(0xff-i, &delta, &d2))
300 break;
301
302 delta -= tsc;
303
304 /*
305 * Extrapolate the error and fail fast if the error will
306 * never be below 500 ppm.
307 */
308 if (i == 1 &&
309 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
310 return 0;
311
312 /*
313 * Iterate until the error is less than 500 ppm
314 */
315 if (d1+d2 >= delta >> 11)
316 continue;
317
318 /*
319 * Check the PIT one more time to verify that
320 * all TSC reads were stable wrt the PIT.
321 *
322 * This also guarantees serialization of the
323 * last cycle read ('d2') in pit_expect_msb.
324 */
325 if (!pit_verify_msb(0xfe - i))
326 break;
327 goto success;
328 }
329 }
330 debug("Fast TSC calibration failed\n");
331 return 0;
332
333 success:
334 /*
335 * Ok, if we get here, then we've seen the
336 * MSB of the PIT decrement 'i' times, and the
337 * error has shrunk to less than 500 ppm.
338 *
339 * As a result, we can depend on there not being
340 * any odd delays anywhere, and the TSC reads are
341 * reliable (within the error).
342 *
343 * kHz = ticks / time-in-seconds / 1000;
344 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
345 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
346 */
347 delta *= PIT_TICK_RATE;
348 delta /= (i*256*1000);
349 debug("Fast TSC calibration using PIT\n");
350 return delta / 1000;
351 }
352
353 /* Get the speed of the TSC timer in MHz */
get_tbclk_mhz(void)354 unsigned notrace long get_tbclk_mhz(void)
355 {
356 return get_tbclk() / 1000000;
357 }
358
get_ms_timer(void)359 static ulong get_ms_timer(void)
360 {
361 return (get_ticks() * 1000) / get_tbclk();
362 }
363
get_timer(ulong base)364 ulong get_timer(ulong base)
365 {
366 return get_ms_timer() - base;
367 }
368
timer_get_us(void)369 ulong notrace timer_get_us(void)
370 {
371 return get_ticks() / get_tbclk_mhz();
372 }
373
timer_get_boot_us(void)374 ulong timer_get_boot_us(void)
375 {
376 return timer_get_us();
377 }
378
__udelay(unsigned long usec)379 void __udelay(unsigned long usec)
380 {
381 u64 now = get_ticks();
382 u64 stop;
383
384 stop = now + (u64)usec * get_tbclk_mhz();
385
386 while ((int64_t)(stop - get_ticks()) > 0)
387 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
388 /*
389 * Add a 'pause' instruction on qemu target,
390 * to give other VCPUs a chance to run.
391 */
392 asm volatile("pause");
393 #else
394 ;
395 #endif
396 }
397
tsc_timer_get_count(struct udevice * dev)398 static u64 tsc_timer_get_count(struct udevice *dev)
399 {
400 u64 now_tick = rdtsc();
401
402 return now_tick - gd->arch.tsc_base;
403 }
404
tsc_timer_ensure_setup(bool early)405 static void tsc_timer_ensure_setup(bool early)
406 {
407 if (gd->arch.tsc_inited)
408 return;
409 if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
410 gd->arch.tsc_base = rdtsc();
411
412 if (!gd->arch.clock_rate) {
413 unsigned long fast_calibrate;
414
415 /* deal with this being called before x86_cpu_init_f() */
416 if (!gd->arch.x86_vendor)
417 x86_get_identity_for_timer();
418
419 /**
420 * There is no obvious way to obtain this information from EFI
421 * boot services. This value was measured on a Framework Laptop
422 * which has a 12th Gen Intel Core
423 */
424 if (IS_ENABLED(CONFIG_EFI_APP)) {
425 fast_calibrate = 2750;
426 goto done;
427 }
428 fast_calibrate = native_calibrate_tsc();
429 if (fast_calibrate)
430 goto done;
431
432 /* Reduce code size by dropping other methods */
433 if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
434 panic("no timer");
435
436 fast_calibrate = cpu_mhz_from_cpuid();
437 if (fast_calibrate)
438 goto done;
439
440 fast_calibrate = cpu_mhz_from_msr();
441 if (fast_calibrate)
442 goto done;
443
444 fast_calibrate = quick_pit_calibrate();
445 if (fast_calibrate)
446 goto done;
447
448 if (early)
449 gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ;
450 else
451 return;
452
453 done:
454 fast_calibrate = min(fast_calibrate, 4000UL);
455 if (!gd->arch.clock_rate)
456 gd->arch.clock_rate = fast_calibrate * 1000000;
457 }
458 gd->arch.tsc_inited = true;
459 }
460
tsc_timer_probe(struct udevice * dev)461 static int tsc_timer_probe(struct udevice *dev)
462 {
463 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
464
465 /* Try hardware calibration first */
466 tsc_timer_ensure_setup(false);
467 if (!gd->arch.clock_rate) {
468 /*
469 * Use the clock frequency specified in the
470 * device tree as last resort
471 */
472 if (!uc_priv->clock_rate)
473 panic("TSC frequency is ZERO");
474 } else {
475 uc_priv->clock_rate = gd->arch.clock_rate;
476 }
477
478 return 0;
479 }
480
timer_early_get_rate(void)481 unsigned long notrace timer_early_get_rate(void)
482 {
483 /*
484 * When TSC timer is used as the early timer, be warned that the timer
485 * clock rate can only be calibrated via some hardware ways. Specifying
486 * it in the device tree won't work for the early timer.
487 */
488 tsc_timer_ensure_setup(true);
489
490 return gd->arch.clock_rate;
491 }
492
timer_early_get_count(void)493 u64 notrace timer_early_get_count(void)
494 {
495 tsc_timer_ensure_setup(true);
496
497 return rdtsc() - gd->arch.tsc_base;
498 }
499
500 static const struct timer_ops tsc_timer_ops = {
501 .get_count = tsc_timer_get_count,
502 };
503
504 #if CONFIG_IS_ENABLED(OF_REAL)
505 static const struct udevice_id tsc_timer_ids[] = {
506 { .compatible = "x86,tsc-timer", },
507 { }
508 };
509 #endif
510
511 U_BOOT_DRIVER(x86_tsc_timer) = {
512 .name = "x86_tsc_timer",
513 .id = UCLASS_TIMER,
514 .of_match = of_match_ptr(tsc_timer_ids),
515 .probe = tsc_timer_probe,
516 .ops = &tsc_timer_ops,
517 };
518