1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * cdns-platform.c - Platform driver for Cadence UFSHCI device
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
6 */
7
8 #include <clk.h>
9 #include <dm.h>
10 #include <ufs.h>
11 #include <asm/io.h>
12 #include <dm/device_compat.h>
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/time.h>
16
17 #include "ufs.h"
18
19 #define CDNS_UFS_REG_HCLKDIV 0xFC
20 #define CDNS_UFS_REG_PHY_XCFGD1 0x113C
21
cdns_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)22 static int cdns_ufs_link_startup_notify(struct ufs_hba *hba,
23 enum ufs_notify_change_status status)
24 {
25 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
26 switch (status) {
27 case PRE_CHANGE:
28 return ufshcd_dme_set(hba,
29 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
30 0);
31 case POST_CHANGE:
32 ;
33 }
34
35 return 0;
36 }
37
cdns_ufs_set_hclkdiv(struct ufs_hba * hba)38 static int cdns_ufs_set_hclkdiv(struct ufs_hba *hba)
39 {
40 struct clk clk;
41 unsigned long core_clk_rate = 0;
42 u32 core_clk_div = 0;
43 int ret;
44
45 ret = clk_get_by_name(hba->dev, "core_clk", &clk);
46 if (ret) {
47 dev_err(hba->dev, "failed to get core_clk clock\n");
48 return ret;
49 }
50
51 core_clk_rate = clk_get_rate(&clk);
52 if (IS_ERR_VALUE(core_clk_rate)) {
53 dev_err(hba->dev, "%s: unable to find core_clk rate\n",
54 __func__);
55 return core_clk_rate;
56 }
57
58 core_clk_div = core_clk_rate / USEC_PER_SEC;
59 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV);
60
61 return 0;
62 }
63
cdns_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)64 static int cdns_ufs_hce_enable_notify(struct ufs_hba *hba,
65 enum ufs_notify_change_status status)
66 {
67 switch (status) {
68 case PRE_CHANGE:
69 return cdns_ufs_set_hclkdiv(hba);
70 case POST_CHANGE:
71 ;
72 }
73
74 return 0;
75 }
76
cdns_ufs_init(struct ufs_hba * hba)77 static int cdns_ufs_init(struct ufs_hba *hba)
78 {
79 u32 data;
80
81 /* Increase RX_Advanced_Min_ActivateTime_Capability */
82 data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1);
83 data |= BIT(24);
84 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1);
85
86 return 0;
87 }
88
89 static struct ufs_hba_ops cdns_pltfm_hba_ops = {
90 .init = cdns_ufs_init,
91 .hce_enable_notify = cdns_ufs_hce_enable_notify,
92 .link_startup_notify = cdns_ufs_link_startup_notify,
93 };
94
cdns_ufs_pltfm_probe(struct udevice * dev)95 static int cdns_ufs_pltfm_probe(struct udevice *dev)
96 {
97 int err = ufshcd_probe(dev, &cdns_pltfm_hba_ops);
98 if (err)
99 dev_err(dev, "ufshcd_probe() failed %d\n", err);
100
101 return err;
102 }
103
cdns_ufs_pltfm_bind(struct udevice * dev)104 static int cdns_ufs_pltfm_bind(struct udevice *dev)
105 {
106 struct udevice *scsi_dev;
107
108 return ufs_scsi_bind(dev, &scsi_dev);
109 }
110
111 static const struct udevice_id cdns_ufs_pltfm_ids[] = {
112 {
113 .compatible = "cdns,ufshc-m31-16nm",
114 },
115 {},
116 };
117
118 U_BOOT_DRIVER(cdns_ufs_pltfm) = {
119 .name = "cdns-ufs-pltfm",
120 .id = UCLASS_UFS,
121 .of_match = cdns_ufs_pltfm_ids,
122 .probe = cdns_ufs_pltfm_probe,
123 .bind = cdns_ufs_pltfm_bind,
124 };
125