1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Generic DWC3 Glue layer
4 *
5 * Copyright (C) 2016 - 2018 Xilinx, Inc.
6 *
7 * Based on dwc3-omap.c.
8 */
9
10 #include <dm.h>
11 #include <reset.h>
12 #include <asm/gpio.h>
13 #include <dm/lists.h>
14 #include <linux/delay.h>
15 #include <linux/usb/gadget.h>
16 #include <power/regulator.h>
17 #include <usb/xhci.h>
18 #include "core.h"
19 #include "dwc3-generic.h"
20 #include "gadget.h"
21
22 struct dwc3_generic_plat {
23 fdt_addr_t base;
24 u32 maximum_speed;
25 enum usb_dr_mode dr_mode;
26 };
27
28 struct dwc3_generic_priv {
29 void *base;
30 struct dwc3 dwc3;
31 struct phy_bulk phys;
32 struct gpio_desc *ulpi_reset;
33 };
34
35 struct dwc3_generic_host_priv {
36 struct xhci_ctrl xhci_ctrl;
37 struct dwc3_generic_priv gen_priv;
38 struct udevice *vbus_supply;
39 };
40
dwc3_generic_probe(struct udevice * dev,struct dwc3_generic_priv * priv,enum usb_dr_mode mode)41 static int dwc3_generic_probe(struct udevice *dev,
42 struct dwc3_generic_priv *priv,
43 enum usb_dr_mode mode)
44 {
45 int rc;
46 struct dwc3_generic_plat *plat = dev_get_plat(dev);
47 struct dwc3 *dwc3 = &priv->dwc3;
48 struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
49 int __maybe_unused index;
50 ofnode __maybe_unused node;
51
52 dwc3->dev = dev;
53 dwc3->maximum_speed = plat->maximum_speed;
54 dwc3->dr_mode = mode;
55 #if CONFIG_IS_ENABLED(OF_CONTROL)
56 dwc3_of_parse(dwc3);
57
58 /*
59 * There are currently four disparate placement possibilities of DWC3
60 * reference clock phandle in SoC DTs:
61 * - in top level glue node, with generic subnode without clock (ZynqMP)
62 * - in top level generic node, with no subnode (i.MX8MQ)
63 * - in generic subnode, with other clock in top level node (i.MX8MP)
64 * - in both top level node and generic subnode (Rockchip)
65 * Cover all the possibilities here by looking into both nodes, start
66 * with the top level node as that seems to be used in majority of DTs
67 * to reference the clock.
68 */
69 node = dev_ofnode(dev->parent);
70 index = ofnode_stringlist_search(node, "clock-names", "ref");
71 if (index < 0)
72 index = ofnode_stringlist_search(node, "clock-names", "ref_clk");
73 if (index < 0) {
74 node = dev_ofnode(dev);
75 index = ofnode_stringlist_search(node, "clock-names", "ref");
76 if (index < 0)
77 index = ofnode_stringlist_search(node, "clock-names", "ref_clk");
78 }
79 if (index >= 0)
80 dwc3->ref_clk = &glue->clks.clks[index];
81 #endif
82
83 /*
84 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
85 * power state in P2 before initializing TypeC PHY on RK3399 platform.
86 */
87 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
88 reset_assert_bulk(&glue->resets);
89 udelay(1);
90 }
91
92 rc = dwc3_setup_phy(dev, &priv->phys);
93 if (rc && rc != -ENOTSUPP)
94 return rc;
95
96 if (CONFIG_IS_ENABLED(DM_GPIO) &&
97 device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) {
98 priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset",
99 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
100 /* property is optional, don't return error! */
101 if (priv->ulpi_reset) {
102 /* Toggle ulpi to reset the phy. */
103 rc = dm_gpio_set_value(priv->ulpi_reset, 1);
104 if (rc)
105 return rc;
106
107 mdelay(5);
108
109 rc = dm_gpio_set_value(priv->ulpi_reset, 0);
110 if (rc)
111 return rc;
112
113 mdelay(5);
114 }
115 }
116
117 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
118 reset_deassert_bulk(&glue->resets);
119
120 priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
121 dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
122
123 rc = dwc3_init(dwc3);
124 if (rc) {
125 unmap_physmem(priv->base, MAP_NOCACHE);
126 return rc;
127 }
128
129 return 0;
130 }
131
dwc3_generic_remove(struct udevice * dev,struct dwc3_generic_priv * priv)132 static int dwc3_generic_remove(struct udevice *dev,
133 struct dwc3_generic_priv *priv)
134 {
135 struct dwc3 *dwc3 = &priv->dwc3;
136
137 if (CONFIG_IS_ENABLED(DM_GPIO) &&
138 device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3") &&
139 priv->ulpi_reset) {
140 struct gpio_desc *ulpi_reset = priv->ulpi_reset;
141
142 dm_gpio_free(ulpi_reset->dev, ulpi_reset);
143 }
144
145 dwc3_remove(dwc3);
146 dwc3_shutdown_phy(dev, &priv->phys);
147 unmap_physmem(dwc3->regs, MAP_NOCACHE);
148
149 return 0;
150 }
151
dwc3_generic_of_to_plat(struct udevice * dev)152 static int dwc3_generic_of_to_plat(struct udevice *dev)
153 {
154 struct dwc3_generic_plat *plat = dev_get_plat(dev);
155 ofnode node = dev_ofnode(dev);
156
157 if (!strncmp(dev->name, "port", 4) || !strncmp(dev->name, "hub", 3)) {
158 /* This is a leaf so check the parent */
159 plat->base = dev_read_addr(dev->parent);
160 } else {
161 plat->base = dev_read_addr(dev);
162 }
163
164 plat->maximum_speed = usb_get_maximum_speed(node);
165 if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
166 pr_info("No USB maximum speed specified. Using super speed\n");
167 plat->maximum_speed = USB_SPEED_SUPER;
168 }
169
170 plat->dr_mode = usb_get_dr_mode(node);
171 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
172 /* might be a leaf so check the parent for mode */
173 node = dev_ofnode(dev->parent);
174 plat->dr_mode = usb_get_dr_mode(node);
175 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
176 pr_err("Invalid usb mode setup\n");
177 return -ENODEV;
178 }
179 }
180
181 return 0;
182 }
183
184 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
dwc3_generic_peripheral_probe(struct udevice * dev)185 static int dwc3_generic_peripheral_probe(struct udevice *dev)
186 {
187 struct dwc3_generic_priv *priv = dev_get_priv(dev);
188
189 return dwc3_generic_probe(dev, priv, USB_DR_MODE_PERIPHERAL);
190 }
191
dwc3_generic_peripheral_remove(struct udevice * dev)192 static int dwc3_generic_peripheral_remove(struct udevice *dev)
193 {
194 struct dwc3_generic_priv *priv = dev_get_priv(dev);
195
196 return dwc3_generic_remove(dev, priv);
197 }
198
dwc3_gadget_handle_interrupts(struct udevice * dev)199 static int dwc3_gadget_handle_interrupts(struct udevice *dev)
200 {
201 struct dwc3_generic_priv *priv = dev_get_priv(dev);
202 struct dwc3 *dwc3 = &priv->dwc3;
203
204 dwc3_gadget_uboot_handle_interrupt(dwc3);
205
206 return 0;
207 }
208
209 static const struct usb_gadget_generic_ops dwc3_gadget_ops = {
210 .handle_interrupts = dwc3_gadget_handle_interrupts,
211 };
212
213 U_BOOT_DRIVER(dwc3_generic_peripheral) = {
214 .name = "dwc3-generic-peripheral",
215 .id = UCLASS_USB_GADGET_GENERIC,
216 .of_to_plat = dwc3_generic_of_to_plat,
217 .ops = &dwc3_gadget_ops,
218 .probe = dwc3_generic_peripheral_probe,
219 .remove = dwc3_generic_peripheral_remove,
220 .priv_auto = sizeof(struct dwc3_generic_priv),
221 .plat_auto = sizeof(struct dwc3_generic_plat),
222 };
223 #endif
224
225 #if CONFIG_IS_ENABLED(USB_HOST)
dwc3_generic_host_probe(struct udevice * dev)226 static int dwc3_generic_host_probe(struct udevice *dev)
227 {
228 struct xhci_hcor *hcor;
229 struct xhci_hccr *hccr;
230 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
231 int rc;
232
233 rc = dwc3_generic_probe(dev, &priv->gen_priv, USB_DR_MODE_HOST);
234 if (rc)
235 return rc;
236
237 rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply);
238 if (rc && rc != -ENOSYS)
239 debug("%s: No vbus regulator found: %d\n", dev->name, rc);
240
241 /* Does not return an error if regulator is invalid - but does so when DM_REGULATOR is disabled */
242 rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
243 if (rc && rc != -ENOSYS)
244 return rc;
245
246 hccr = (struct xhci_hccr *)priv->gen_priv.base;
247 hcor = (struct xhci_hcor *)(priv->gen_priv.base +
248 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
249
250 rc = xhci_register(dev, hccr, hcor);
251 if (rc)
252 regulator_set_enable_if_allowed(priv->vbus_supply, false);
253
254 return rc;
255 }
256
dwc3_generic_host_remove(struct udevice * dev)257 static int dwc3_generic_host_remove(struct udevice *dev)
258 {
259 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
260 int rc;
261
262 /* This function always returns 0 */
263 xhci_deregister(dev);
264
265 rc = regulator_set_enable_if_allowed(priv->vbus_supply, false);
266 if (rc)
267 debug("%s: Failed to disable vbus regulator: %d\n", dev->name, rc);
268
269 return dwc3_generic_remove(dev, &priv->gen_priv);
270 }
271
272 U_BOOT_DRIVER(dwc3_generic_host) = {
273 .name = "dwc3-generic-host",
274 .id = UCLASS_USB,
275 .of_to_plat = dwc3_generic_of_to_plat,
276 .probe = dwc3_generic_host_probe,
277 .remove = dwc3_generic_host_remove,
278 .priv_auto = sizeof(struct dwc3_generic_host_priv),
279 .plat_auto = sizeof(struct dwc3_generic_plat),
280 .ops = &xhci_usb_ops,
281 .flags = DM_FLAG_ALLOC_PRIV_DMA,
282 };
283 #endif
284
dwc3_imx8mp_glue_configure(struct udevice * dev,int index,enum usb_dr_mode mode)285 void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
286 enum usb_dr_mode mode)
287 {
288 /* USB glue registers */
289 #define USB_CTRL0 0x00
290 #define USB_CTRL1 0x04
291
292 #define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
293 #define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
294 #define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
295
296 #define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
297 #define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
298 fdt_addr_t regs = dev_read_addr_index(dev, 1);
299 void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
300 u32 value;
301
302 value = readl(base + USB_CTRL0);
303
304 if (dev_read_bool(dev, "fsl,permanently-attached"))
305 value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
306 else
307 value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
308
309 if (dev_read_bool(dev, "fsl,disable-port-power-control"))
310 value &= ~(USB_CTRL0_PORTPWR_EN);
311 else
312 value |= USB_CTRL0_PORTPWR_EN;
313
314 writel(value, base + USB_CTRL0);
315
316 value = readl(base + USB_CTRL1);
317 if (dev_read_bool(dev, "fsl,over-current-active-low"))
318 value |= USB_CTRL1_OC_POLARITY;
319 else
320 value &= ~USB_CTRL1_OC_POLARITY;
321
322 if (dev_read_bool(dev, "fsl,power-active-low"))
323 value |= USB_CTRL1_PWR_POLARITY;
324 else
325 value &= ~USB_CTRL1_PWR_POLARITY;
326
327 writel(value, base + USB_CTRL1);
328
329 unmap_physmem(base, MAP_NOCACHE);
330 }
331
332 struct dwc3_glue_ops imx8mp_ops = {
333 .glue_configure = dwc3_imx8mp_glue_configure,
334 };
335
dwc3_ti_glue_configure(struct udevice * dev,int index,enum usb_dr_mode mode)336 void dwc3_ti_glue_configure(struct udevice *dev, int index,
337 enum usb_dr_mode mode)
338 {
339 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
340 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
341
342 /* UTMI_OTG_STATUS REGISTER */
343 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
344 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
345 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
346 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
347 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
348 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
349 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
350 enum dwc3_omap_utmi_mode {
351 DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
352 DWC3_OMAP_UTMI_MODE_HW,
353 DWC3_OMAP_UTMI_MODE_SW,
354 };
355
356 u32 use_id_pin;
357 u32 host_mode;
358 u32 reg;
359 u32 utmi_mode;
360 u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
361
362 struct dwc3_glue_data *glue = dev_get_plat(dev);
363 void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
364
365 if (device_is_compatible(dev, "ti,am437x-dwc3"))
366 utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
367
368 utmi_mode = dev_read_u32_default(dev, "utmi-mode",
369 DWC3_OMAP_UTMI_MODE_UNKNOWN);
370 if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
371 debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
372 dev->name);
373 mode = USB_DR_MODE_PERIPHERAL;
374 }
375
376 switch (mode) {
377 case USB_DR_MODE_PERIPHERAL:
378 use_id_pin = 0;
379 host_mode = 0;
380 break;
381 case USB_DR_MODE_HOST:
382 use_id_pin = 0;
383 host_mode = 1;
384 break;
385 case USB_DR_MODE_OTG:
386 default:
387 use_id_pin = 1;
388 host_mode = 0;
389 break;
390 }
391
392 reg = readl(base + utmi_status_offset);
393
394 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
395 if (!use_id_pin)
396 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
397
398 writel(reg, base + utmi_status_offset);
399
400 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
401 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
402 USBOTGSS_UTMI_OTG_STATUS_IDDIG);
403
404 reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
405 USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
406
407 if (!host_mode)
408 reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
409 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
410
411 writel(reg, base + utmi_status_offset);
412
413 unmap_physmem(base, MAP_NOCACHE);
414 }
415
416 struct dwc3_glue_ops ti_ops = {
417 .glue_configure = dwc3_ti_glue_configure,
418 };
419
420 /* USB QSCRATCH Hardware registers */
421 #define QSCRATCH_GENERAL_CFG 0x08
422 #define PIPE_UTMI_CLK_SEL BIT(0)
423 #define PIPE3_PHYSTATUS_SW BIT(3)
424 #define PIPE_UTMI_CLK_DIS BIT(8)
425
426 #define QSCRATCH_HS_PHY_CTRL 0x10
427 #define UTMI_OTG_VBUS_VALID BIT(20)
428 #define SW_SESSVLD_SEL BIT(28)
429
430 #define QSCRATCH_SS_PHY_CTRL 0x30
431 #define LANE0_PWR_PRESENT BIT(24)
432
433 #define PWR_EVNT_IRQ_STAT_REG 0x58
434 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
435 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
436
437 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
438 #define SDM845_QSCRATCH_SIZE 0x400
439 #define SDM845_DWC3_CORE_SIZE 0xcd00
440
dwc3_qcom_vbus_override_enable(void __iomem * qscratch_base,bool enable)441 static void dwc3_qcom_vbus_override_enable(void __iomem *qscratch_base, bool enable)
442 {
443 if (enable) {
444 setbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
445 LANE0_PWR_PRESENT);
446 setbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
447 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
448 } else {
449 clrbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
450 LANE0_PWR_PRESENT);
451 clrbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
452 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
453 }
454 }
455
456 /* For controllers running without superspeed PHYs */
dwc3_qcom_select_utmi_clk(void __iomem * qscratch_base)457 static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
458 {
459 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
460 setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
461 PIPE_UTMI_CLK_DIS);
462
463 setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
464 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
465
466 clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
467 PIPE_UTMI_CLK_DIS);
468 }
469
dwc3_qcom_glue_configure(struct udevice * dev,int index,enum usb_dr_mode mode)470 static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
471 enum usb_dr_mode mode)
472 {
473 struct dwc3_glue_data *glue = dev_get_plat(dev);
474 void __iomem *qscratch_base = map_physmem(glue->regs, 0x400, MAP_NOCACHE);
475 if (IS_ERR_OR_NULL(qscratch_base)) {
476 log_err("%s: Invalid qscratch base address\n", dev->name);
477 return;
478 }
479
480 if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
481 dwc3_qcom_select_utmi_clk(qscratch_base);
482
483 if (mode != USB_DR_MODE_HOST)
484 dwc3_qcom_vbus_override_enable(qscratch_base, true);
485 }
486
487 struct dwc3_glue_ops qcom_ops = {
488 .glue_configure = dwc3_qcom_glue_configure,
489 };
490
dwc3_rk_glue_get_ctrl_dev(struct udevice * dev,ofnode * node)491 static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
492 {
493 *node = dev_ofnode(dev);
494 if (!ofnode_valid(*node))
495 return -EINVAL;
496
497 return 0;
498 }
499
500 struct dwc3_glue_ops rk_ops = {
501 .glue_get_ctrl_dev = dwc3_rk_glue_get_ctrl_dev,
502 };
503
dwc3_glue_bind_common(struct udevice * parent,ofnode node)504 static int dwc3_glue_bind_common(struct udevice *parent, ofnode node)
505 {
506 const char *name = ofnode_get_name(node);
507 const char *driver;
508 enum usb_dr_mode dr_mode;
509 struct udevice *dev;
510 int ret;
511
512 debug("%s: subnode name: %s\n", __func__, name);
513
514 /* if the parent node doesn't have a mode check the leaf */
515 dr_mode = usb_get_dr_mode(dev_ofnode(parent));
516 if (!dr_mode)
517 dr_mode = usb_get_dr_mode(node);
518
519 if (CONFIG_IS_ENABLED(DM_USB_GADGET) &&
520 (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) {
521 debug("%s: dr_mode: OTG or Peripheral\n", __func__);
522 driver = "dwc3-generic-peripheral";
523 } else if (CONFIG_IS_ENABLED(USB_HOST) && dr_mode == USB_DR_MODE_HOST) {
524 debug("%s: dr_mode: HOST\n", __func__);
525 driver = "dwc3-generic-host";
526 } else {
527 debug("%s: unsupported dr_mode %d\n", __func__, dr_mode);
528 return -ENODEV;
529 }
530
531 ret = device_bind_driver_to_node(parent, driver, name,
532 node, &dev);
533 if (ret) {
534 debug("%s: not able to bind usb device mode\n",
535 __func__);
536 return ret;
537 }
538
539 return 0;
540 }
541
dwc3_glue_bind(struct udevice * parent)542 int dwc3_glue_bind(struct udevice *parent)
543 {
544 struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(parent);
545 ofnode node;
546 int ret;
547
548 if (ops && ops->glue_get_ctrl_dev) {
549 ret = ops->glue_get_ctrl_dev(parent, &node);
550 if (ret)
551 return ret;
552
553 return dwc3_glue_bind_common(parent, node);
554 }
555
556 ofnode_for_each_subnode(node, dev_ofnode(parent)) {
557 ret = dwc3_glue_bind_common(parent, node);
558 if (ret == -ENXIO)
559 continue;
560 if (ret)
561 return ret;
562 }
563
564 return 0;
565 }
566
dwc3_glue_reset_init(struct udevice * dev,struct dwc3_glue_data * glue)567 static int dwc3_glue_reset_init(struct udevice *dev,
568 struct dwc3_glue_data *glue)
569 {
570 int ret;
571
572 ret = reset_get_bulk(dev, &glue->resets);
573 if (ret == -ENOTSUPP || ret == -ENOENT)
574 return 0;
575 else if (ret)
576 return ret;
577
578 if (device_is_compatible(dev, "qcom,dwc3")) {
579 reset_assert_bulk(&glue->resets);
580 /* We should wait at least 6 sleep clock cycles, that's
581 * (6 / 32764) * 1000000 ~= 200us. But some platforms
582 * have slower sleep clocks so we'll play it safe.
583 */
584 udelay(500);
585 }
586 ret = reset_deassert_bulk(&glue->resets);
587 if (ret) {
588 reset_release_bulk(&glue->resets);
589 return ret;
590 }
591
592 return 0;
593 }
594
dwc3_glue_clk_init(struct udevice * dev,struct dwc3_glue_data * glue)595 static int dwc3_glue_clk_init(struct udevice *dev,
596 struct dwc3_glue_data *glue)
597 {
598 int ret;
599
600 ret = clk_get_bulk(dev, &glue->clks);
601 if (ret == -ENOSYS || ret == -ENOENT)
602 return 0;
603 if (ret)
604 return ret;
605
606 #if CONFIG_IS_ENABLED(CLK)
607 ret = clk_enable_bulk(&glue->clks);
608 if (ret) {
609 clk_release_bulk(&glue->clks);
610 return ret;
611 }
612 #endif
613
614 return 0;
615 }
616
dwc3_glue_probe(struct udevice * dev)617 int dwc3_glue_probe(struct udevice *dev)
618 {
619 struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
620 struct dwc3_glue_data *glue = dev_get_plat(dev);
621 struct udevice *child = NULL;
622 int index = 0;
623 int ret;
624 struct phy phy;
625
626 ret = generic_phy_get_by_name(dev, "usb3-phy", &phy);
627 if (!ret) {
628 ret = generic_phy_init(&phy);
629 if (ret)
630 return ret;
631 } else if (ret != -ENOENT && ret != -ENODATA) {
632 debug("could not get phy (err %d)\n", ret);
633 return ret;
634 }
635
636 glue->regs = dev_read_addr_size_index(dev, 0, &glue->size);
637
638 ret = dwc3_glue_clk_init(dev, glue);
639 if (ret)
640 return ret;
641
642 ret = dwc3_glue_reset_init(dev, glue);
643 if (ret)
644 return ret;
645
646 if (generic_phy_valid(&phy)) {
647 ret = generic_phy_power_on(&phy);
648 if (ret)
649 return ret;
650 }
651
652 device_find_first_child(dev, &child);
653 if (!child)
654 return 0;
655
656 if (glue->clks.count == 0) {
657 ret = dwc3_glue_clk_init(child, glue);
658 if (ret)
659 return ret;
660 }
661
662 if (glue->resets.count == 0) {
663 ret = dwc3_glue_reset_init(child, glue);
664 if (ret)
665 return ret;
666 }
667
668 while (child) {
669 enum usb_dr_mode dr_mode;
670
671 dr_mode = usb_get_dr_mode(dev_ofnode(child));
672 device_find_next_child(&child);
673 if (ops && ops->glue_configure)
674 ops->glue_configure(dev, index, dr_mode);
675 index++;
676 }
677
678 return 0;
679 }
680
dwc3_glue_remove(struct udevice * dev)681 int dwc3_glue_remove(struct udevice *dev)
682 {
683 struct dwc3_glue_data *glue = dev_get_plat(dev);
684
685 reset_release_bulk(&glue->resets);
686
687 clk_release_bulk(&glue->clks);
688
689 return 0;
690 }
691
692 static const struct udevice_id dwc3_glue_ids[] = {
693 { .compatible = "xlnx,zynqmp-dwc3" },
694 { .compatible = "xlnx,versal-dwc3" },
695 { .compatible = "ti,keystone-dwc3"},
696 { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
697 { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
698 { .compatible = "ti,am654-dwc3" },
699 { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
700 { .compatible = "rockchip,rk3399-dwc3" },
701 { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
702 { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
703 { .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
704 { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
705 { .compatible = "fsl,imx8mq-dwc3" },
706 { .compatible = "intel,tangier-dwc3" },
707 { .compatible = "samsung,exynos850-dwusb3" },
708 { }
709 };
710
711 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
712 .name = "dwc3-generic-wrapper",
713 .id = UCLASS_NOP,
714 .of_match = dwc3_glue_ids,
715 .bind = dwc3_glue_bind,
716 .probe = dwc3_glue_probe,
717 .remove = dwc3_glue_remove,
718 .plat_auto = sizeof(struct dwc3_glue_data),
719
720 };
721