1 /* SPDX-License-Identifier: GPL-1.0+ */ 2 /* 3 * Renesas USB driver 4 * 5 * Copyright (C) 2011 Renesas Solutions Corp. 6 * Copyright (C) 2019 Renesas Electronics Corporation 7 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 8 */ 9 #ifndef RENESAS_USB_DRIVER_H 10 #define RENESAS_USB_DRIVER_H 11 12 #include <dm/device.h> 13 #include <dm/device_compat.h> 14 #include <linux/bug.h> 15 #include <linux/delay.h> 16 #include <linux/io.h> 17 #include "renesas_usb.h" 18 19 struct usbhs_priv; 20 21 #include "mod.h" 22 #include "pipe.h" 23 24 /* 25 * 26 * register define 27 * 28 */ 29 #define SYSCFG 0x0000 30 #define BUSWAIT 0x0002 31 #define DVSTCTR 0x0008 32 #define TESTMODE 0x000C 33 #define CFIFO 0x0014 34 #define CFIFOSEL 0x0020 35 #define CFIFOCTR 0x0022 36 #define D0FIFO 0x0100 37 #define D0FIFOSEL 0x0028 38 #define D0FIFOCTR 0x002A 39 #define D1FIFO 0x0120 40 #define D1FIFOSEL 0x002C 41 #define D1FIFOCTR 0x002E 42 #define INTENB0 0x0030 43 #define INTENB1 0x0032 44 #define BRDYENB 0x0036 45 #define NRDYENB 0x0038 46 #define BEMPENB 0x003A 47 #define INTSTS0 0x0040 48 #define INTSTS1 0x0042 49 #define BRDYSTS 0x0046 50 #define NRDYSTS 0x0048 51 #define BEMPSTS 0x004A 52 #define FRMNUM 0x004C 53 #define USBREQ 0x0054 /* USB request type register */ 54 #define USBVAL 0x0056 /* USB request value register */ 55 #define USBINDX 0x0058 /* USB request index register */ 56 #define USBLENG 0x005A /* USB request length register */ 57 #define DCPCFG 0x005C 58 #define DCPMAXP 0x005E 59 #define DCPCTR 0x0060 60 #define PIPESEL 0x0064 61 #define PIPECFG 0x0068 62 #define PIPEBUF 0x006A 63 #define PIPEMAXP 0x006C 64 #define PIPEPERI 0x006E 65 #define PIPEnCTR 0x0070 66 #define PIPE1TRE 0x0090 67 #define PIPE1TRN 0x0092 68 #define PIPE2TRE 0x0094 69 #define PIPE2TRN 0x0096 70 #define PIPE3TRE 0x0098 71 #define PIPE3TRN 0x009A 72 #define PIPE4TRE 0x009C 73 #define PIPE4TRN 0x009E 74 #define PIPE5TRE 0x00A0 75 #define PIPE5TRN 0x00A2 76 #define PIPEBTRE 0x00A4 77 #define PIPEBTRN 0x00A6 78 #define PIPECTRE 0x00A8 79 #define PIPECTRN 0x00AA 80 #define PIPEDTRE 0x00AC 81 #define PIPEDTRN 0x00AE 82 #define PIPEETRE 0x00B0 83 #define PIPEETRN 0x00B2 84 #define PIPEFTRE 0x00B4 85 #define PIPEFTRN 0x00B6 86 #define PIPE9TRE 0x00B8 87 #define PIPE9TRN 0x00BA 88 #define PIPEATRE 0x00BC 89 #define PIPEATRN 0x00BE 90 #define DEVADD0 0x00D0 /* Device address n configuration */ 91 #define DEVADD1 0x00D2 92 #define DEVADD2 0x00D4 93 #define DEVADD3 0x00D6 94 #define DEVADD4 0x00D8 95 #define DEVADD5 0x00DA 96 #define DEVADD6 0x00DC 97 #define DEVADD7 0x00DE 98 #define DEVADD8 0x00E0 99 #define DEVADD9 0x00E2 100 #define DEVADDA 0x00E4 101 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */ 102 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */ 103 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */ 104 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */ 105 #define SUSPMODE 0x0102 /* for RZ/A */ 106 107 /* SYSCFG */ 108 #define SCKE (1 << 10) /* USB Module Clock Enable */ 109 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */ 110 #define HSE (1 << 7) /* High-Speed Operation Enable */ 111 #define DCFM (1 << 6) /* Controller Function Select */ 112 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */ 113 #define DPRPU (1 << 4) /* D+ Line Resistance Control */ 114 #define USBE (1 << 0) /* USB Module Operation Enable */ 115 #define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */ 116 #define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */ 117 118 /* DVSTCTR */ 119 #define EXTLP (1 << 10) /* Controls the EXTLP pin output state */ 120 #define PWEN (1 << 9) /* Controls the PWEN pin output state */ 121 #define USBRST (1 << 6) /* Bus Reset Output */ 122 #define UACT (1 << 4) /* USB Bus Enable */ 123 #define RHST (0x7) /* Reset Handshake */ 124 #define RHST_LOW_SPEED 1 /* Low-speed connection */ 125 #define RHST_FULL_SPEED 2 /* Full-speed connection */ 126 #define RHST_HIGH_SPEED 3 /* High-speed connection */ 127 128 /* CFIFOSEL */ 129 #define DREQE (1 << 12) /* DMA Transfer Request Enable */ 130 #define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */ 131 132 /* CFIFOCTR */ 133 #define BVAL (1 << 15) /* Buffer Memory Enable Flag */ 134 #define BCLR (1 << 14) /* CPU buffer clear */ 135 #define FRDY (1 << 13) /* FIFO Port Ready */ 136 #define DTLN_MASK (0x0FFF) /* Receive Data Length */ 137 138 /* INTENB0 */ 139 #define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */ 140 #define RSME (1 << 14) /* Enable IRQ Resume */ 141 #define SOFE (1 << 13) /* Enable IRQ Frame Number Update */ 142 #define DVSE (1 << 12) /* Enable IRQ Device State Transition */ 143 #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */ 144 #define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */ 145 #define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */ 146 #define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */ 147 148 /* INTENB1 */ 149 #define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */ 150 #define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */ 151 #define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */ 152 #define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */ 153 #define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */ 154 #define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */ 155 156 /* INTSTS0 */ 157 #define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */ 158 #define DVST (1 << 12) /* Device State Transition Interrupt Status */ 159 #define CTRT (1 << 11) /* Control Stage Interrupt Status */ 160 #define BEMP (1 << 10) /* Buffer Empty Interrupt Status */ 161 #define BRDY (1 << 8) /* Buffer Ready Interrupt Status */ 162 #define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */ 163 #define VALID (1 << 3) /* USB Request Receive */ 164 165 #define DVSQ_MASK (0x7 << 4) /* Device State */ 166 #define POWER_STATE (0 << 4) 167 #define DEFAULT_STATE (1 << 4) 168 #define ADDRESS_STATE (2 << 4) 169 #define CONFIGURATION_STATE (3 << 4) 170 #define SUSPENDED_STATE (4 << 4) 171 172 #define CTSQ_MASK (0x7) /* Control Transfer Stage */ 173 #define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */ 174 #define READ_DATA_STAGE 1 /* Control read data stage */ 175 #define READ_STATUS_STAGE 2 /* Control read status stage */ 176 #define WRITE_DATA_STAGE 3 /* Control write data stage */ 177 #define WRITE_STATUS_STAGE 4 /* Control write status stage */ 178 #define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */ 179 #define SEQUENCE_ERROR 6 /* Control transfer sequence error */ 180 181 /* INTSTS1 */ 182 #define OVRCR (1 << 15) /* OVRCR Interrupt Status */ 183 #define BCHG (1 << 14) /* USB Bus Change Interrupt Status */ 184 #define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */ 185 #define ATTCH (1 << 11) /* ATTCH Interrupt Status */ 186 #define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */ 187 #define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */ 188 #define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */ 189 190 /* PIPECFG */ 191 /* DCPCFG */ 192 #define TYPE_NONE (0 << 14) /* Transfer Type */ 193 #define TYPE_BULK (1 << 14) 194 #define TYPE_INT (2 << 14) 195 #define TYPE_ISO (3 << 14) 196 #define BFRE (1 << 10) /* BRDY Interrupt Operation Spec. */ 197 #define DBLB (1 << 9) /* Double Buffer Mode */ 198 #define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */ 199 #define DIR_OUT (1 << 4) /* Transfer Direction */ 200 201 /* PIPEMAXP */ 202 /* DCPMAXP */ 203 #define DEVSEL_MASK (0xF << 12) /* Device Select */ 204 #define DCP_MAXP_MASK (0x7F) 205 #define PIPE_MAXP_MASK (0x7FF) 206 207 /* PIPEBUF */ 208 #define BUFSIZE_SHIFT 10 209 #define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT) 210 #define BUFNMB_MASK (0xFF) 211 212 /* PIPEnCTR */ 213 /* DCPCTR */ 214 #define BSTS (1 << 15) /* Buffer Status */ 215 #define SUREQ (1 << 14) /* Sending SETUP Token */ 216 #define INBUFM (1 << 14) /* (PIPEnCTR) Transfer Buffer Monitor */ 217 #define CSSTS (1 << 12) /* CSSTS Status */ 218 #define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */ 219 #define SQCLR (1 << 8) /* Toggle Bit Clear */ 220 #define SQSET (1 << 7) /* Toggle Bit Set */ 221 #define SQMON (1 << 6) /* Toggle Bit Check */ 222 #define PBUSY (1 << 5) /* Pipe Busy */ 223 #define PID_MASK (0x3) /* Response PID */ 224 #define PID_NAK 0 225 #define PID_BUF 1 226 #define PID_STALL10 2 227 #define PID_STALL11 3 228 229 #define CCPL (1 << 2) /* Control Transfer End Enable */ 230 231 /* PIPEnTRE */ 232 #define TRENB (1 << 9) /* Transaction Counter Enable */ 233 #define TRCLR (1 << 8) /* Transaction Counter Clear */ 234 235 /* FRMNUM */ 236 #define FRNM_MASK (0x7FF) 237 238 /* DEVADDn */ 239 #define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */ 240 #define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */ 241 #define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */ 242 #define USBSPD_SPEED_LOW 0x1 243 #define USBSPD_SPEED_FULL 0x2 244 #define USBSPD_SPEED_HIGH 0x3 245 246 /* SUSPMODE */ 247 #define SUSPM (1 << 14) /* SuspendM Control */ 248 249 /* 250 * struct 251 */ 252 struct usbhs_priv { 253 void __iomem *base; 254 struct renesas_usbhs_driver_param dparam; 255 struct platform_device *pdev; 256 257 /* 258 * module control 259 */ 260 struct usbhs_mod_info mod_info; 261 262 /* 263 * pipe control 264 */ 265 struct usbhs_pipe_info pipe_info; 266 267 /* 268 * fifo control 269 */ 270 struct usbhs_fifo_info fifo_info; 271 }; 272 273 /* 274 * common 275 */ 276 u16 usbhs_read(struct usbhs_priv *priv, u32 reg); 277 void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data); 278 void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data); 279 280 #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f) 281 #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f) 282 283 /* 284 * sysconfig 285 */ 286 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable); 287 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable); 288 void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable); 289 void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode); 290 291 /* 292 * usb request 293 */ 294 void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 295 void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 296 297 /* 298 * bus 299 */ 300 void usbhs_bus_send_sof_enable(struct usbhs_priv *priv); 301 void usbhs_bus_send_reset(struct usbhs_priv *priv); 302 int usbhs_bus_get_speed(struct usbhs_priv *priv); 303 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable); 304 void usbhsc_hotplug(struct usbhs_priv *priv); 305 306 /* 307 * frame 308 */ 309 int usbhs_frame_get_num(struct usbhs_priv *priv); 310 311 /* 312 * device config 313 */ 314 int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub, 315 u16 hubport, u16 speed); 316 317 /* 318 * interrupt functions 319 */ 320 void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit); 321 322 /* 323 * data 324 */ 325 #define usbhs_get_dparam(priv, param) (priv->dparam.param) 326 #define usbhs_priv_to_dev(priv) (&priv->pdev->dev) 327 328 #endif /* RENESAS_USB_DRIVER_H */ 329