1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 4 */ 5 6 #ifndef __DWC2_H__ 7 #define __DWC2_H__ 8 9 /* Host controller specific */ 10 #define DWC2_HC_PID_DATA0 0 11 #define DWC2_HC_PID_DATA2 1 12 #define DWC2_HC_PID_DATA1 2 13 #define DWC2_HC_PID_MDATA 3 14 #define DWC2_HC_PID_SETUP 3 15 16 /* roothub.a masks */ 17 #define RH_A_NDP GENMASK(7, 0) /* number of downstream ports */ 18 #define RH_A_PSM BIT(8) /* power switching mode */ 19 #define RH_A_NPS BIT(9) /* no power switching */ 20 #define RH_A_DT BIT(10) /* device type (mbz) */ 21 #define RH_A_OCPM BIT(11) /* over current protection mode */ 22 #define RH_A_NOCP BIT(12) /* no over current protection */ 23 #define RH_A_POTPGT GENMASK(31, 24) /* power on to power good time */ 24 25 /* roothub.b masks */ 26 #define RH_B_DR 0x0000ffff /* device removable flags */ 27 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 28 29 /* Default driver configuration */ 30 #define DWC2_DMA_ENABLE 31 #define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ 32 #undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ 33 #define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ 34 #define DWC2_MAX_CHANNELS 16 /* Max # of EPs */ 35 #define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS) 36 #define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ 37 #define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ 38 #define DWC2_MAX_TRANSFER_SIZE 65535 39 #define DWC2_MAX_PACKET_COUNT 511 40 41 #define DWC2_PHY_TYPE_FS 0 42 #define DWC2_PHY_TYPE_UTMI 1 43 #define DWC2_PHY_TYPE_ULPI 2 44 #define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ 45 #ifndef DWC2_UTMI_WIDTH 46 #define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ 47 #endif 48 49 #undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ 50 #define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ 51 #undef DWC2_I2C_ENABLE /* Enable I2C */ 52 #undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */ 53 #undef DWC2_TS_DLINE /* External DLine pulsing */ 54 #undef DWC2_THR_CTL /* Threshold control */ 55 #define DWC2_TX_THR_LENGTH 64 56 #undef DWC2_IC_USB_CAP /* IC Cap */ 57 58 #endif /* __DWC2_H__ */ 59