1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
6 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
7 *
8 * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
9 * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
10 */
11
12 #include <clk.h>
13 #include <dsi_host.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <panel.h>
17 #include <video.h>
18 #include <asm/io.h>
19 #include <dm/device-internal.h>
20 #include <dm/device_compat.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/iopoll.h>
24 #include <linux/time.h>
25 #include <video_bridge.h>
26
27 #define HWVER_131 0x31333100 /* IP version 1.31 */
28
29 #define DSI_VERSION 0x00
30 #define VERSION GENMASK(31, 8)
31
32 #define DSI_PWR_UP 0x04
33 #define RESET 0
34 #define POWERUP BIT(0)
35
36 #define DSI_CLKMGR_CFG 0x08
37 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
38 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
39
40 #define DSI_DPI_VCID 0x0c
41 #define DPI_VCID(vcid) ((vcid) & 0x3)
42
43 #define DSI_DPI_COLOR_CODING 0x10
44 #define LOOSELY18_EN BIT(8)
45 #define DPI_COLOR_CODING_16BIT_1 0x0
46 #define DPI_COLOR_CODING_16BIT_2 0x1
47 #define DPI_COLOR_CODING_16BIT_3 0x2
48 #define DPI_COLOR_CODING_18BIT_1 0x3
49 #define DPI_COLOR_CODING_18BIT_2 0x4
50 #define DPI_COLOR_CODING_24BIT 0x5
51
52 #define DSI_DPI_CFG_POL 0x14
53 #define COLORM_ACTIVE_LOW BIT(4)
54 #define SHUTD_ACTIVE_LOW BIT(3)
55 #define HSYNC_ACTIVE_LOW BIT(2)
56 #define VSYNC_ACTIVE_LOW BIT(1)
57 #define DATAEN_ACTIVE_LOW BIT(0)
58
59 #define DSI_DPI_LP_CMD_TIM 0x18
60 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
61 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
62
63 #define DSI_DBI_VCID 0x1c
64 #define DSI_DBI_CFG 0x20
65 #define DSI_DBI_PARTITIONING_EN 0x24
66 #define DSI_DBI_CMDSIZE 0x28
67
68 #define DSI_PCKHDL_CFG 0x2c
69 #define CRC_RX_EN BIT(4)
70 #define ECC_RX_EN BIT(3)
71 #define BTA_EN BIT(2)
72 #define EOTP_RX_EN BIT(1)
73 #define EOTP_TX_EN BIT(0)
74
75 #define DSI_GEN_VCID 0x30
76
77 #define DSI_MODE_CFG 0x34
78 #define ENABLE_VIDEO_MODE 0
79 #define ENABLE_CMD_MODE BIT(0)
80
81 #define DSI_VID_MODE_CFG 0x38
82 #define ENABLE_LOW_POWER (0x3f << 8)
83 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
84 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
85 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
86 #define VID_MODE_TYPE_BURST 0x2
87 #define VID_MODE_TYPE_MASK 0x3
88
89 #define DSI_VID_PKT_SIZE 0x3c
90 #define VID_PKT_SIZE(p) ((p) & 0x3fff)
91
92 #define DSI_VID_NUM_CHUNKS 0x40
93 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
94
95 #define DSI_VID_NULL_SIZE 0x44
96 #define VID_NULL_SIZE(b) ((b) & 0x1fff)
97
98 #define DSI_VID_HSA_TIME 0x48
99 #define DSI_VID_HBP_TIME 0x4c
100 #define DSI_VID_HLINE_TIME 0x50
101 #define DSI_VID_VSA_LINES 0x54
102 #define DSI_VID_VBP_LINES 0x58
103 #define DSI_VID_VFP_LINES 0x5c
104 #define DSI_VID_VACTIVE_LINES 0x60
105 #define DSI_EDPI_CMD_SIZE 0x64
106
107 #define DSI_CMD_MODE_CFG 0x68
108 #define MAX_RD_PKT_SIZE_LP BIT(24)
109 #define DCS_LW_TX_LP BIT(19)
110 #define DCS_SR_0P_TX_LP BIT(18)
111 #define DCS_SW_1P_TX_LP BIT(17)
112 #define DCS_SW_0P_TX_LP BIT(16)
113 #define GEN_LW_TX_LP BIT(14)
114 #define GEN_SR_2P_TX_LP BIT(13)
115 #define GEN_SR_1P_TX_LP BIT(12)
116 #define GEN_SR_0P_TX_LP BIT(11)
117 #define GEN_SW_2P_TX_LP BIT(10)
118 #define GEN_SW_1P_TX_LP BIT(9)
119 #define GEN_SW_0P_TX_LP BIT(8)
120 #define ACK_RQST_EN BIT(1)
121 #define TEAR_FX_EN BIT(0)
122
123 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
124 DCS_LW_TX_LP | \
125 DCS_SR_0P_TX_LP | \
126 DCS_SW_1P_TX_LP | \
127 DCS_SW_0P_TX_LP | \
128 GEN_LW_TX_LP | \
129 GEN_SR_2P_TX_LP | \
130 GEN_SR_1P_TX_LP | \
131 GEN_SR_0P_TX_LP | \
132 GEN_SW_2P_TX_LP | \
133 GEN_SW_1P_TX_LP | \
134 GEN_SW_0P_TX_LP)
135
136 #define DSI_GEN_HDR 0x6c
137 #define DSI_GEN_PLD_DATA 0x70
138
139 #define DSI_CMD_PKT_STATUS 0x74
140 #define GEN_RD_CMD_BUSY BIT(6)
141 #define GEN_PLD_R_FULL BIT(5)
142 #define GEN_PLD_R_EMPTY BIT(4)
143 #define GEN_PLD_W_FULL BIT(3)
144 #define GEN_PLD_W_EMPTY BIT(2)
145 #define GEN_CMD_FULL BIT(1)
146 #define GEN_CMD_EMPTY BIT(0)
147
148 #define DSI_TO_CNT_CFG 0x78
149 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
150 #define LPRX_TO_CNT(p) ((p) & 0xffff)
151
152 #define DSI_HS_RD_TO_CNT 0x7c
153 #define DSI_LP_RD_TO_CNT 0x80
154 #define DSI_HS_WR_TO_CNT 0x84
155 #define DSI_LP_WR_TO_CNT 0x88
156 #define DSI_BTA_TO_CNT 0x8c
157
158 #define DSI_LPCLK_CTRL 0x94
159 #define AUTO_CLKLANE_CTRL BIT(1)
160 #define PHY_TXREQUESTCLKHS BIT(0)
161
162 #define DSI_PHY_TMR_LPCLK_CFG 0x98
163 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
164 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
165
166 #define DSI_PHY_TMR_CFG 0x9c
167 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
168 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
169 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
170 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
171 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
172
173 #define DSI_PHY_RSTZ 0xa0
174 #define PHY_DISFORCEPLL 0
175 #define PHY_ENFORCEPLL BIT(3)
176 #define PHY_DISABLECLK 0
177 #define PHY_ENABLECLK BIT(2)
178 #define PHY_RSTZ 0
179 #define PHY_UNRSTZ BIT(1)
180 #define PHY_SHUTDOWNZ 0
181 #define PHY_UNSHUTDOWNZ BIT(0)
182
183 #define DSI_PHY_IF_CFG 0xa4
184 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
185 #define N_LANES(n) (((n) - 1) & 0x3)
186
187 #define DSI_PHY_ULPS_CTRL 0xa8
188 #define DSI_PHY_TX_TRIGGERS 0xac
189
190 #define DSI_PHY_STATUS 0xb0
191 #define PHY_STOP_STATE_CLK_LANE BIT(2)
192 #define PHY_LOCK BIT(0)
193
194 #define DSI_PHY_TST_CTRL0 0xb4
195 #define PHY_TESTCLK BIT(1)
196 #define PHY_UNTESTCLK 0
197 #define PHY_TESTCLR BIT(0)
198 #define PHY_UNTESTCLR 0
199
200 #define DSI_PHY_TST_CTRL1 0xb8
201 #define PHY_TESTEN BIT(16)
202 #define PHY_UNTESTEN 0
203 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
204 #define PHY_TESTDIN(n) ((n) & 0xff)
205
206 #define DSI_INT_ST0 0xbc
207 #define DSI_INT_ST1 0xc0
208 #define DSI_INT_MSK0 0xc4
209 #define DSI_INT_MSK1 0xc8
210
211 #define DSI_PHY_TMR_RD_CFG 0xf4
212 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
213
214 #define PHY_STATUS_TIMEOUT_US 10000
215 #define CMD_PKT_STATUS_TIMEOUT_US 20000
216
217 struct dw_mipi_dsi {
218 struct mipi_dsi_host dsi_host;
219 struct mipi_dsi_device *device;
220 void __iomem *base;
221 unsigned int lane_mbps; /* per lane */
222 u32 channel;
223 unsigned int max_data_lanes;
224 const struct mipi_dsi_phy_ops *phy_ops;
225 };
226
dsi_mode_vrefresh(struct display_timing * timings)227 static int dsi_mode_vrefresh(struct display_timing *timings)
228 {
229 int refresh = 0;
230 unsigned int calc_val;
231 u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
232 timings->hback_porch.typ + timings->hsync_len.typ;
233 u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
234 timings->vback_porch.typ + timings->vsync_len.typ;
235
236 if (htotal > 0 && vtotal > 0) {
237 calc_val = timings->pixelclock.typ;
238 calc_val /= htotal;
239 refresh = (calc_val + vtotal / 2) / vtotal;
240 }
241
242 return refresh;
243 }
244
245 /*
246 * The controller should generate 2 frames before
247 * preparing the peripheral.
248 */
dw_mipi_dsi_wait_for_two_frames(struct display_timing * timings)249 static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
250 {
251 int refresh, two_frames;
252
253 refresh = dsi_mode_vrefresh(timings);
254 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
255 mdelay(two_frames);
256 }
257
host_to_dsi(struct mipi_dsi_host * host)258 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
259 {
260 return container_of(host, struct dw_mipi_dsi, dsi_host);
261 }
262
dsi_write(struct dw_mipi_dsi * dsi,u32 reg,u32 val)263 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
264 {
265 writel(val, dsi->base + reg);
266 }
267
dsi_read(struct dw_mipi_dsi * dsi,u32 reg)268 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
269 {
270 return readl(dsi->base + reg);
271 }
272
dw_mipi_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)273 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
274 struct mipi_dsi_device *device)
275 {
276 struct dw_mipi_dsi *dsi = host_to_dsi(host);
277
278 if (device->lanes > dsi->max_data_lanes) {
279 dev_err(device->dev,
280 "the number of data lanes(%u) is too many\n",
281 device->lanes);
282 return -EINVAL;
283 }
284
285 dsi->channel = device->channel;
286
287 return 0;
288 }
289
dw_mipi_message_config(struct dw_mipi_dsi * dsi,const struct mipi_dsi_msg * msg)290 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
291 const struct mipi_dsi_msg *msg)
292 {
293 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
294 u32 val = 0;
295
296 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
297 val |= ACK_RQST_EN;
298 if (lpm)
299 val |= CMD_MODE_ALL_LP;
300
301 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
302 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
303 }
304
dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi * dsi,u32 hdr_val)305 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
306 {
307 int ret;
308 u32 val, mask;
309
310 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
311 val, !(val & GEN_CMD_FULL),
312 CMD_PKT_STATUS_TIMEOUT_US);
313 if (ret) {
314 dev_err(dsi->dsi_host.dev,
315 "failed to get available command FIFO\n");
316 return ret;
317 }
318
319 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
320
321 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
322 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
323 val, (val & mask) == mask,
324 CMD_PKT_STATUS_TIMEOUT_US);
325 if (ret) {
326 dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n");
327 return ret;
328 }
329
330 return 0;
331 }
332
dw_mipi_dsi_write(struct dw_mipi_dsi * dsi,const struct mipi_dsi_packet * packet)333 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
334 const struct mipi_dsi_packet *packet)
335 {
336 const u8 *tx_buf = packet->payload;
337 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
338 __le32 word;
339 u32 val;
340
341 while (len) {
342 if (len < pld_data_bytes) {
343 word = 0;
344 memcpy(&word, tx_buf, len);
345 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
346 len = 0;
347 } else {
348 memcpy(&word, tx_buf, pld_data_bytes);
349 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
350 tx_buf += pld_data_bytes;
351 len -= pld_data_bytes;
352 }
353
354 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
355 val, !(val & GEN_PLD_W_FULL),
356 CMD_PKT_STATUS_TIMEOUT_US);
357 if (ret) {
358 dev_err(dsi->dsi_host.dev,
359 "failed to get available write payload FIFO\n");
360 return ret;
361 }
362 }
363
364 word = 0;
365 memcpy(&word, packet->header, sizeof(packet->header));
366 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
367 }
368
dw_mipi_dsi_read(struct dw_mipi_dsi * dsi,const struct mipi_dsi_msg * msg)369 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
370 const struct mipi_dsi_msg *msg)
371 {
372 int i, j, ret, len = msg->rx_len;
373 u8 *buf = msg->rx_buf;
374 u32 val;
375
376 /* Wait end of the read operation */
377 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
378 val, !(val & GEN_RD_CMD_BUSY),
379 CMD_PKT_STATUS_TIMEOUT_US);
380 if (ret) {
381 dev_err(dsi->dsi_host.dev, "Timeout during read operation\n");
382 return ret;
383 }
384
385 for (i = 0; i < len; i += 4) {
386 /* Read fifo must not be empty before all bytes are read */
387 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
388 val, !(val & GEN_PLD_R_EMPTY),
389 CMD_PKT_STATUS_TIMEOUT_US);
390 if (ret) {
391 dev_err(dsi->dsi_host.dev,
392 "Read payload FIFO is empty\n");
393 return ret;
394 }
395
396 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
397 for (j = 0; j < 4 && j + i < len; j++)
398 buf[i + j] = val >> (8 * j);
399 }
400
401 return ret;
402 }
403
dw_mipi_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)404 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
405 const struct mipi_dsi_msg *msg)
406 {
407 struct dw_mipi_dsi *dsi = host_to_dsi(host);
408 struct mipi_dsi_packet packet;
409 int ret, nb_bytes;
410
411 ret = mipi_dsi_create_packet(&packet, msg);
412 if (ret) {
413 dev_err(host->dev, "failed to create packet: %d\n", ret);
414 return ret;
415 }
416
417 dw_mipi_message_config(dsi, msg);
418
419 ret = dw_mipi_dsi_write(dsi, &packet);
420 if (ret)
421 return ret;
422
423 if (msg->rx_buf && msg->rx_len) {
424 ret = dw_mipi_dsi_read(dsi, msg);
425 if (ret)
426 return ret;
427 nb_bytes = msg->rx_len;
428 } else {
429 nb_bytes = packet.size;
430 }
431
432 return nb_bytes;
433 }
434
435 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
436 .attach = dw_mipi_dsi_host_attach,
437 .transfer = dw_mipi_dsi_host_transfer,
438 };
439
dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi * dsi)440 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
441 {
442 struct mipi_dsi_device *device = dsi->device;
443 u32 val;
444
445 /*
446 * TODO dw drv improvements
447 * enabling low power is panel-dependent, we should use the
448 * panel configuration here...
449 */
450 val = ENABLE_LOW_POWER;
451
452 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
453 val |= VID_MODE_TYPE_BURST;
454 else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
455 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
456 else
457 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
458
459 dsi_write(dsi, DSI_VID_MODE_CFG, val);
460 }
461
dw_mipi_dsi_set_mode(struct dw_mipi_dsi * dsi,unsigned long mode_flags)462 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
463 unsigned long mode_flags)
464 {
465 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
466
467 dsi_write(dsi, DSI_PWR_UP, RESET);
468
469 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
470 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
471 dw_mipi_dsi_video_mode_config(dsi);
472 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
473 } else {
474 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
475 }
476
477 if (phy_ops->post_set_mode)
478 phy_ops->post_set_mode(dsi->device, mode_flags);
479
480 dsi_write(dsi, DSI_PWR_UP, POWERUP);
481 }
482
dw_mipi_dsi_init_pll(struct dw_mipi_dsi * dsi)483 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
484 {
485 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
486 unsigned int esc_rate;
487 u32 esc_clk_division;
488
489 /*
490 * The maximum permitted escape clock is 20MHz and it is derived from
491 * lanebyteclk, which is running at "lane_mbps / 8".
492 */
493 if (phy_ops->get_esc_clk_rate)
494 phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
495 else
496 esc_rate = 20; /* Default to 20MHz */
497
498 /*
499 * We want:
500 *
501 * (lane_mbps >> 3) / esc_clk_division < X
502 * which is:
503 * (lane_mbps >> 3) / X > esc_clk_division
504 */
505 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
506
507 dsi_write(dsi, DSI_PWR_UP, RESET);
508
509 /*
510 * TODO dw drv improvements
511 * timeout clock division should be computed with the
512 * high speed transmission counter timeout and byte lane...
513 */
514 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
515 TX_ESC_CLK_DIVISION(esc_clk_division));
516 }
517
dw_mipi_dsi_dpi_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)518 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
519 struct display_timing *timings)
520 {
521 struct mipi_dsi_device *device = dsi->device;
522 u32 val = 0, color = 0;
523
524 switch (device->format) {
525 case MIPI_DSI_FMT_RGB888:
526 color = DPI_COLOR_CODING_24BIT;
527 break;
528 case MIPI_DSI_FMT_RGB666:
529 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
530 break;
531 case MIPI_DSI_FMT_RGB666_PACKED:
532 color = DPI_COLOR_CODING_18BIT_1;
533 break;
534 case MIPI_DSI_FMT_RGB565:
535 color = DPI_COLOR_CODING_16BIT_1;
536 break;
537 }
538
539 if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW)
540 val |= VSYNC_ACTIVE_LOW;
541 if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW)
542 val |= HSYNC_ACTIVE_LOW;
543
544 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
545 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
546 dsi_write(dsi, DSI_DPI_CFG_POL, val);
547 /*
548 * TODO dw drv improvements
549 * largest packet sizes during hfp or during vsa/vpb/vfp
550 * should be computed according to byte lane, lane number and only
551 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
552 */
553 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
554 | INVACT_LPCMD_TIME(4));
555 }
556
dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi * dsi)557 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
558 {
559 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
560 }
561
dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)562 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
563 struct display_timing *timings)
564 {
565 /*
566 * TODO dw drv improvements
567 * only burst mode is supported here. For non-burst video modes,
568 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
569 * DSI_VNPCR.NPSIZE... especially because this driver supports
570 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
571 */
572 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
573 }
574
dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi * dsi)575 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
576 {
577 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
578
579 /*
580 * TODO dw drv improvements
581 * compute high speed transmission counter timeout according
582 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
583 */
584 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
585 /*
586 * TODO dw drv improvements
587 * the Bus-Turn-Around Timeout Counter should be computed
588 * according to byte lane...
589 */
590 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
591 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
592
593 if (phy_ops->post_set_mode)
594 phy_ops->post_set_mode(dsi->device, 0);
595 }
596
597 /* Get lane byte clock cycles. */
dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi * dsi,struct display_timing * timings,u32 hcomponent)598 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
599 struct display_timing *timings,
600 u32 hcomponent)
601 {
602 u32 frac, lbcc;
603
604 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
605
606 frac = lbcc % (timings->pixelclock.typ / 1000);
607 lbcc = lbcc / (timings->pixelclock.typ / 1000);
608 if (frac)
609 lbcc++;
610
611 return lbcc;
612 }
613
dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)614 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
615 struct display_timing *timings)
616 {
617 u32 htotal, hsa, hbp, lbcc;
618
619 htotal = timings->hactive.typ + timings->hfront_porch.typ +
620 timings->hback_porch.typ + timings->hsync_len.typ;
621
622 hsa = timings->hsync_len.typ;
623 hbp = timings->hback_porch.typ;
624
625 /*
626 * TODO dw drv improvements
627 * computations below may be improved...
628 */
629 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
630 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
631
632 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
633 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
634
635 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
636 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
637 }
638
dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi * dsi,struct display_timing * timings)639 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
640 struct display_timing *timings)
641 {
642 u32 vactive, vsa, vfp, vbp;
643
644 vactive = timings->vactive.typ;
645 vsa = timings->vsync_len.typ;
646 vfp = timings->vfront_porch.typ;
647 vbp = timings->vback_porch.typ;
648
649 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
650 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
651 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
652 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
653 }
654
dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi * dsi)655 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
656 {
657 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
658 struct mipi_dsi_phy_timing timing = {0x40, 0x40, 0x40, 0x40};
659 u32 hw_version;
660
661 if (phy_ops->get_timing)
662 phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing);
663
664 /*
665 * TODO dw drv improvements
666 * data & clock lane timers should be computed according to panel
667 * blankings and to the automatic clock lane control mode...
668 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
669 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
670 */
671
672 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
673
674 if (hw_version >= HWVER_131) {
675 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
676 PHY_LP2HS_TIME_V131(timing.data_lp2hs));
677 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
678 } else {
679 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) |
680 PHY_LP2HS_TIME(timing.data_lp2hs) | MAX_RD_TIME(10000));
681 }
682
683 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp)
684 | PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
685 }
686
dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi * dsi)687 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
688 {
689 struct mipi_dsi_device *device = dsi->device;
690
691 /*
692 * TODO dw drv improvements
693 * stop wait time should be the maximum between host dsi
694 * and panel stop wait times
695 */
696 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
697 N_LANES(device->lanes));
698 }
699
dw_mipi_dsi_dphy_init(struct dw_mipi_dsi * dsi)700 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
701 {
702 /* Clear PHY state */
703 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
704 | PHY_RSTZ | PHY_SHUTDOWNZ);
705 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
706 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
707 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
708 }
709
dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi * dsi)710 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
711 {
712 u32 val;
713 int ret;
714
715 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
716 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
717
718 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
719 val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
720 if (ret)
721 dev_dbg(dsi->dsi_host.dev,
722 "failed to wait phy lock state\n");
723
724 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
725 val, val & PHY_STOP_STATE_CLK_LANE,
726 PHY_STATUS_TIMEOUT_US);
727 if (ret)
728 dev_dbg(dsi->dsi_host.dev,
729 "failed to wait phy clk lane stop state\n");
730 }
731
dw_mipi_dsi_clear_err(struct dw_mipi_dsi * dsi)732 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
733 {
734 dsi_read(dsi, DSI_INT_ST0);
735 dsi_read(dsi, DSI_INT_ST1);
736 dsi_write(dsi, DSI_INT_MSK0, 0);
737 dsi_write(dsi, DSI_INT_MSK1, 0);
738 }
739
dw_mipi_dsi_bridge_set(struct dw_mipi_dsi * dsi,struct display_timing * timings)740 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
741 struct display_timing *timings)
742 {
743 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
744 struct mipi_dsi_device *device = dsi->device;
745 int ret;
746
747 ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
748 device->format, &dsi->lane_mbps);
749 if (ret)
750 dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n");
751
752 dw_mipi_dsi_init_pll(dsi);
753 dw_mipi_dsi_dpi_config(dsi, timings);
754 dw_mipi_dsi_packet_handler_config(dsi);
755 dw_mipi_dsi_video_mode_config(dsi);
756 dw_mipi_dsi_video_packet_config(dsi, timings);
757 dw_mipi_dsi_command_mode_config(dsi);
758 dw_mipi_dsi_line_timer_config(dsi, timings);
759 dw_mipi_dsi_vertical_timing_config(dsi, timings);
760
761 dw_mipi_dsi_dphy_init(dsi);
762 dw_mipi_dsi_dphy_timing_config(dsi);
763 dw_mipi_dsi_dphy_interface_config(dsi);
764
765 dw_mipi_dsi_clear_err(dsi);
766
767 ret = phy_ops->init(dsi->device);
768 if (ret)
769 dev_warn(dsi->dsi_host.dev, "Phy init() failed\n");
770
771 dw_mipi_dsi_dphy_enable(dsi);
772
773 dw_mipi_dsi_wait_for_two_frames(timings);
774
775 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
776 dw_mipi_dsi_set_mode(dsi, 0);
777 }
778
dw_mipi_dsi_init(struct udevice * dev,struct mipi_dsi_device * device,struct display_timing * timings,unsigned int max_data_lanes,const struct mipi_dsi_phy_ops * phy_ops)779 static int dw_mipi_dsi_init(struct udevice *dev,
780 struct mipi_dsi_device *device,
781 struct display_timing *timings,
782 unsigned int max_data_lanes,
783 const struct mipi_dsi_phy_ops *phy_ops)
784 {
785 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
786 struct clk clk;
787 int ret;
788
789 if (!phy_ops->init || !phy_ops->get_lane_mbps) {
790 dev_err(device->dev, "Phy not properly configured\n");
791 return -ENODEV;
792 }
793
794 dsi->phy_ops = phy_ops;
795 dsi->max_data_lanes = max_data_lanes;
796 dsi->device = device;
797 dsi->dsi_host.dev = (struct device *)dev;
798 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
799 device->host = &dsi->dsi_host;
800
801 dsi->base = dev_read_addr_ptr(device->dev);
802 if (!dsi->base) {
803 dev_err(device->dev, "dsi dt register address error\n");
804 return -EINVAL;
805 }
806
807 /*
808 * The Rockchip based devices don't have px_clk, so simply move
809 * on.
810 */
811 if (IS_ENABLED(CONFIG_DISPLAY_ROCKCHIP_DW_MIPI)) {
812 dw_mipi_dsi_bridge_set(dsi, timings);
813 return 0;
814 }
815
816 ret = clk_get_by_name(device->dev, "px_clk", &clk);
817 if (ret) {
818 dev_err(device->dev, "peripheral clock get error %d\n", ret);
819 return ret;
820 }
821
822 /* get the pixel clock set by the clock framework */
823 timings->pixelclock.typ = clk_get_rate(&clk);
824
825 dw_mipi_dsi_bridge_set(dsi, timings);
826
827 return 0;
828 }
829
dw_mipi_dsi_enable(struct udevice * dev)830 static int dw_mipi_dsi_enable(struct udevice *dev)
831 {
832 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
833
834 /* Switch to video mode for panel-bridge enable & panel enable */
835 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
836
837 return 0;
838 }
839
840 struct dsi_host_ops dw_mipi_dsi_ops = {
841 .init = dw_mipi_dsi_init,
842 .enable = dw_mipi_dsi_enable,
843 };
844
dw_mipi_dsi_probe(struct udevice * dev)845 static int dw_mipi_dsi_probe(struct udevice *dev)
846 {
847 return 0;
848 }
849
850 U_BOOT_DRIVER(dw_mipi_dsi) = {
851 .name = "dw_mipi_dsi",
852 .id = UCLASS_DSI_HOST,
853 .probe = dw_mipi_dsi_probe,
854 .ops = &dw_mipi_dsi_ops,
855 .priv_auto = sizeof(struct dw_mipi_dsi),
856 };
857
858 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
859 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
860 MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
861 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
862 MODULE_LICENSE("GPL");
863 MODULE_ALIAS("platform:dw-mipi-dsi");
864