1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _TEGRA_DC_H 8 #define _TEGRA_DC_H 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 /* arch-tegra/dc exists only because T124 uses it */ 15 #include <asm/arch-tegra/dc.h> 16 17 struct tegra_dc_plat { 18 struct udevice *dev; /* Display controller device */ 19 struct dc_ctlr *dc; /* Display controller regmap */ 20 int pipe; /* DC number: 0 for A, 1 for B */ 21 ulong scdiv; /* Shift clock divider */ 22 }; 23 24 /* This holds information about a window which can be displayed */ 25 struct disp_ctl_win { 26 enum win_color_depth_id fmt; /* Color depth/format */ 27 unsigned int bpp; /* Bits per pixel */ 28 phys_addr_t phys_addr; /* Physical address in memory */ 29 unsigned int x; /* Horizontal address offset (bytes) */ 30 unsigned int y; /* Veritical address offset (bytes) */ 31 unsigned int w; /* Width of source window */ 32 unsigned int h; /* Height of source window */ 33 unsigned int stride; /* Number of bytes per line */ 34 unsigned int out_x; /* Left edge of output window (col) */ 35 unsigned int out_y; /* Top edge of output window (row) */ 36 unsigned int out_w; /* Width of output window in pixels */ 37 unsigned int out_h; /* Height of output window in pixels */ 38 }; 39 40 #endif /* _TEGRA_DC_H */ 41