1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A83t EMAC
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13properties:
14  compatible:
15    oneOf:
16      - const: allwinner,sun8i-a83t-emac
17      - const: allwinner,sun8i-h3-emac
18      - const: allwinner,sun8i-r40-gmac
19      - const: allwinner,sun8i-v3s-emac
20      - const: allwinner,sun50i-a64-emac
21      - items:
22          - enum:
23              - allwinner,sun20i-d1-emac
24              - allwinner,sun50i-h6-emac
25              - allwinner,sun50i-h616-emac0
26              - allwinner,sun55i-a523-gmac0
27          - const: allwinner,sun50i-a64-emac
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  interrupt-names:
36    const: macirq
37
38  clocks:
39    maxItems: 1
40
41  clock-names:
42    const: stmmaceth
43
44  phy-supply:
45    description: PHY regulator
46
47  syscon:
48    $ref: /schemas/types.yaml#/definitions/phandle
49    description:
50      Phandle to the device containing the EMAC or GMAC clock
51      register
52
53required:
54  - compatible
55  - reg
56  - interrupts
57  - interrupt-names
58  - clocks
59  - clock-names
60  - resets
61  - reset-names
62  - phy-handle
63  - phy-mode
64  - syscon
65
66allOf:
67  - $ref: snps,dwmac.yaml#
68  - if:
69      properties:
70        compatible:
71          contains:
72            enum:
73              - allwinner,sun8i-a83t-emac
74              - allwinner,sun8i-h3-emac
75              - allwinner,sun8i-v3s-emac
76              - allwinner,sun50i-a64-emac
77
78    then:
79      properties:
80        allwinner,tx-delay-ps:
81          default: 0
82          minimum: 0
83          maximum: 700
84          multipleOf: 100
85          description:
86            External RGMII PHY TX clock delay chain value in ps.
87
88        allwinner,rx-delay-ps:
89          default: 0
90          minimum: 0
91          maximum: 3100
92          multipleOf: 100
93          description:
94            External RGMII PHY TX clock delay chain value in ps.
95
96  - if:
97      properties:
98        compatible:
99          contains:
100            enum:
101              - allwinner,sun8i-r40-gmac
102
103    then:
104      properties:
105        allwinner,rx-delay-ps:
106          default: 0
107          minimum: 0
108          maximum: 700
109          multipleOf: 100
110          description:
111            External RGMII PHY TX clock delay chain value in ps.
112
113  - if:
114      properties:
115        compatible:
116          contains:
117            enum:
118              - allwinner,sun8i-h3-emac
119              - allwinner,sun8i-v3s-emac
120
121    then:
122      properties:
123        allwinner,leds-active-low:
124          $ref: /schemas/types.yaml#/definitions/flag
125          description:
126            EPHY LEDs are active low.
127
128        mdio-mux:
129          type: object
130          unevaluatedProperties: false
131
132          properties:
133            compatible:
134              const: allwinner,sun8i-h3-mdio-mux
135
136            mdio-parent-bus:
137              $ref: /schemas/types.yaml#/definitions/phandle
138              description:
139                Phandle to EMAC MDIO.
140
141            "#address-cells":
142              const: 1
143
144            "#size-cells":
145              const: 0
146
147            mdio@1:
148              $ref: mdio.yaml#
149              unevaluatedProperties: false
150              description: Internal MDIO Bus
151
152              properties:
153                compatible:
154                  const: allwinner,sun8i-h3-mdio-internal
155
156                reg:
157                  const: 1
158
159              patternProperties:
160                "^ethernet-phy@[0-9a-f]$":
161                  type: object
162                  $ref: ethernet-phy.yaml#
163                  unevaluatedProperties: false
164                  description:
165                    Integrated PHY node
166
167                  properties:
168                    clocks:
169                      maxItems: 1
170
171                    resets:
172                      maxItems: 1
173
174                  required:
175                    - clocks
176                    - resets
177
178
179            mdio@2:
180              $ref: mdio.yaml#
181              unevaluatedProperties: false
182              description: External MDIO Bus (H3 only)
183
184              properties:
185                reg:
186                  const: 2
187
188          required:
189            - compatible
190            - mdio-parent-bus
191            - mdio@1
192
193unevaluatedProperties: false
194
195examples:
196  - |
197    ethernet@1c0b000 {
198        compatible = "allwinner,sun8i-h3-emac";
199        syscon = <&syscon>;
200        reg = <0x01c0b000 0x104>;
201        interrupts = <0 82 1>;
202        interrupt-names = "macirq";
203        resets = <&ccu 12>;
204        reset-names = "stmmaceth";
205        clocks = <&ccu 27>;
206        clock-names = "stmmaceth";
207
208        phy-handle = <&int_mii_phy>;
209        phy-mode = "mii";
210        allwinner,leds-active-low;
211
212        mdio1: mdio {
213            #address-cells = <1>;
214            #size-cells = <0>;
215            compatible = "snps,dwmac-mdio";
216        };
217
218        mdio-mux {
219            compatible = "allwinner,sun8i-h3-mdio-mux";
220            #address-cells = <1>;
221            #size-cells = <0>;
222
223            mdio-parent-bus = <&mdio1>;
224
225            int_mii_phy: mdio@1 {
226                compatible = "allwinner,sun8i-h3-mdio-internal";
227                reg = <1>;
228                #address-cells = <1>;
229                #size-cells = <0>;
230
231                ethernet-phy@1 {
232                    reg = <1>;
233                    clocks = <&ccu 67>;
234                    resets = <&ccu 39>;
235                    phy-is-integrated;
236                };
237            };
238
239            mdio@2 {
240                reg = <2>;
241                #address-cells = <1>;
242                #size-cells = <0>;
243            };
244        };
245    };
246
247  - |
248    ethernet@1c0b000 {
249        compatible = "allwinner,sun8i-h3-emac";
250        syscon = <&syscon>;
251        reg = <0x01c0b000 0x104>;
252        interrupts = <0 82 1>;
253        interrupt-names = "macirq";
254        resets = <&ccu 12>;
255        reset-names = "stmmaceth";
256        clocks = <&ccu 27>;
257        clock-names = "stmmaceth";
258
259        phy-handle = <&ext_rgmii_phy>;
260        phy-mode = "rgmii";
261        allwinner,leds-active-low;
262
263        mdio2: mdio {
264            #address-cells = <1>;
265            #size-cells = <0>;
266            compatible = "snps,dwmac-mdio";
267        };
268
269        mdio-mux {
270            compatible = "allwinner,sun8i-h3-mdio-mux";
271            #address-cells = <1>;
272            #size-cells = <0>;
273            mdio-parent-bus = <&mdio2>;
274
275            mdio@1 {
276                compatible = "allwinner,sun8i-h3-mdio-internal";
277                reg = <1>;
278                #address-cells = <1>;
279                #size-cells = <0>;
280
281                ethernet-phy@1 {
282                    reg = <1>;
283                    clocks = <&ccu 67>;
284                    resets = <&ccu 39>;
285                };
286            };
287
288            mdio@2 {
289                reg = <2>;
290                #address-cells = <1>;
291                #size-cells = <0>;
292
293                ext_rgmii_phy: ethernet-phy@1 {
294                    reg = <1>;
295                };
296            };
297        };
298    };
299
300  - |
301    ethernet@1c0b000 {
302        compatible = "allwinner,sun8i-a83t-emac";
303        syscon = <&syscon>;
304        reg = <0x01c0b000 0x104>;
305        interrupts = <0 82 1>;
306        interrupt-names = "macirq";
307        resets = <&ccu 13>;
308        reset-names = "stmmaceth";
309        clocks = <&ccu 27>;
310        clock-names = "stmmaceth";
311        phy-handle = <&ext_rgmii_phy1>;
312        phy-mode = "rgmii";
313
314        mdio {
315            compatible = "snps,dwmac-mdio";
316            #address-cells = <1>;
317            #size-cells = <0>;
318
319            ext_rgmii_phy1: ethernet-phy@1 {
320                reg = <1>;
321            };
322        };
323    };
324
325...
326